ARM: uniphier: disable cache in SPL of PH1-LD20
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Tue, 24 May 2016 12:13:57 +0000 (21:13 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Wed, 25 May 2016 15:35:26 +0000 (00:35 +0900)
commit0bd20207ab2d874842161cab37c213310d785b24
treeda95cd1c624176e51bd12a9b709e968afd89205f
parentfc15b9beed05dec6cc092c265042381a0eadb0e9
ARM: uniphier: disable cache in SPL of PH1-LD20

The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table.  Disable D-cache and MMU
before jumping to U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm/mach-uniphier/init/init-ld20.c