drm/i915/ringbuffer: Move double invalidate to after pd flush
authorChris Wilson <chris@chris-wilson.co.uk>
Tue, 4 Sep 2018 06:38:02 +0000 (07:38 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 4 Sep 2018 13:28:51 +0000 (14:28 +0100)
commit06348d3086a3b34f2db6c7692b4327fb7fc0b6c7
treef15737e60f0a24bffc56a92e0e67f4bd589ff578
parent7ef4ac6ed9eddd12c48020998d98647d2d85bdb1
drm/i915/ringbuffer: Move double invalidate to after pd flush

Continuing the fun of trying to find exactly the delay that is
sufficient to ensure that the page directory is fully loaded between
context switches, move the extra flush added in commit 70b73f9ac113
("drm/i915/ringbuffer: Delay after invalidating gen6+ xcs") to just
after we flush the pd. Entirely based on the empirical data of running
failing tests in a loop until we survive a day (before the mtbf is 10-30
minutes).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107769
References: 70b73f9ac113 ("drm/i915/ringbuffer: Delay after invalidating gen6+ xcs")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180904063802.13880-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/intel_ringbuffer.c