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(parent: f28ff06) | patch
drm/amdgpu:Add DPG mode read/write macro
authorJames Zhu <James.Zhu@amd.com>
Mon, 10 Sep 2018 20:00:36 +0000 (16:00 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Sep 2018 02:09:24 +0000 (21:09 -0500)
commit03d6e3aac81634a91dd2790f8c199ffb3927fe3c
tree1c6e343575897cebfc58612cff171b91092c12detree | snapshot
parentf28ff06210f444da0b52168450625ad883ff8a1fcommit | diff
drm/amdgpu:Add DPG mode read/write macro

Some registers read/write needs program through SDRAM pool under
DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/soc15_common.h diff | blob | history
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