git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 5149901e9e6deca487c01cc434a3ac4125c7b00b Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Mon, 15 Jun 2020 23:06:03 +0200
   4 Subject: PCI: qcom: Define some PARF params needed for ipq8064 SoC
   5
   6 Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
   7 needed on some ipq8064 based device (Netgear R7800 for example). Without
   8 this the system locks on kernel load.
   9
  10 Link: https://lore.kernel.org/r/20200615210608.21469-8-ansuelsmth@gmail.com
  11 Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
  12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  13 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  14 Reviewed-by: Rob Herring <robh@kernel.org>
  15 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  16 Cc: stable@vger.kernel.org # v4.5+
  17 ---
  18  drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++++++++
  19  1 file changed, 24 insertions(+)
  20
  21 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  22 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  23 @@ -76,6 +76,18 @@
  24  #define DBI_RO_WR_EN                           1
  25
  26  #define PERST_DELAY_US                         1000
  27 +/* PARF registers */
  28 +#define PCIE20_PARF_PCS_DEEMPH                 0x34
  29 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)           ((x) << 16)
  30 +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)     ((x) << 8)
  31 +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)       ((x) << 0)
  32 +
  33 +#define PCIE20_PARF_PCS_SWING                  0x38
  34 +#define PCS_SWING_TX_SWING_FULL(x)             ((x) << 8)
  35 +#define PCS_SWING_TX_SWING_LOW(x)              ((x) << 0)
  36 +
  37 +#define PCIE20_PARF_CONFIG_BITS                0x50
  38 +#define PHY_RX0_EQ(x)                          ((x) << 24)
  39
  40  #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE     0x358
  41  #define SLV_ADDR_SPACE_SZ                      0x10000000
  42 @@ -282,6 +294,7 @@ static int qcom_pcie_init_2_1_0(struct q
  43         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
  44         struct dw_pcie *pci = pcie->pci;
  45         struct device *dev = pci->dev;
  46 +       struct device_node *node = dev->of_node;
  47         u32 val;
  48         int ret;
  49
  50 @@ -336,6 +349,17 @@ static int qcom_pcie_init_2_1_0(struct q
  51         val &= ~BIT(0);
  52         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
  53
  54 +       if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
  55 +               writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
  56 +                              PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
  57 +                              PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
  58 +                      pcie->parf + PCIE20_PARF_PCS_DEEMPH);
  59 +               writel(PCS_SWING_TX_SWING_FULL(120) |
  60 +                              PCS_SWING_TX_SWING_LOW(120),
  61 +                      pcie->parf + PCIE20_PARF_PCS_SWING);
  62 +               writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
  63 +       }
  64 +
  65         /* enable external reference clock */
  66         val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
  67         val |= BIT(16);