fd9e9e2c482fdd9a53e797b9f38a01666edbfee5
[openwrt/staging/rmilecki.git] /
1 From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
2 From: Miquel Raynal <miquel.raynal@bootlin.com>
3 Date: Thu, 27 Jan 2022 10:18:01 +0100
4 Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
5 structure
6
7 Soon the SPI-NAND core will need a way to request a SPI controller to
8 enable ECC support for a given operation. This is because of the
9 pipelined integration of certain ECC engines, which are directly managed
10 by the SPI controller itself.
11
12 Introduce a spi_mem_op additional field for this purpose: ecc.
13
14 So far this field is left unset and checked to be false by all
15 the SPI controller drivers in their ->supports_op() hook, as they all
16 call spi_mem_default_supports_op().
17
18 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
19 Acked-by: Pratyush Yadav <p.yadav@ti.com>
20 Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
21 Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
22 Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com
23 (cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
24 ---
25 drivers/spi/spi-mem.c | 5 +++++
26 include/linux/spi/spi-mem.h | 4 ++++
27 2 files changed, 9 insertions(+)
28
29 diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
30 index ed966d8129eb..f38ac31961c9 100644
31 --- a/drivers/spi/spi-mem.c
32 +++ b/drivers/spi/spi-mem.c
33 @@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
34 return false;
35 }
36
37 + if (op->data.ecc) {
38 + if (!spi_mem_controller_is_capable(ctlr, ecc))
39 + return false;
40 + }
41 +
42 return spi_mem_check_buswidth(mem, op);
43 }
44 EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
45 diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
46 index 4a1bfe689872..2ba044d0d5e5 100644
47 --- a/include/linux/spi/spi-mem.h
48 +++ b/include/linux/spi/spi-mem.h
49 @@ -89,6 +89,7 @@ enum spi_mem_data_dir {
50 * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
51 * @data.buswidth: number of IO lanes used to send/receive the data
52 * @data.dtr: whether the data should be sent in DTR mode or not
53 + * @data.ecc: whether error correction is required or not
54 * @data.dir: direction of the transfer
55 * @data.nbytes: number of data bytes to send/receive. Can be zero if the
56 * operation does not involve transferring data
57 @@ -119,6 +120,7 @@ struct spi_mem_op {
58 struct {
59 u8 buswidth;
60 u8 dtr : 1;
61 + u8 ecc : 1;
62 enum spi_mem_data_dir dir;
63 unsigned int nbytes;
64 union {
65 @@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
66 /**
67 * struct spi_controller_mem_caps - SPI memory controller capabilities
68 * @dtr: Supports DTR operations
69 + * @ecc: Supports operations with error correction
70 */
71 struct spi_controller_mem_caps {
72 bool dtr;
73 + bool ecc;
74 };
75
76 #define spi_mem_controller_is_capable(ctlr, cap) \
77 --
78 2.35.1
79