projects / openwrt / staging / stintel.git / blob
? search:


fc8f95566697a4a61920010d7dd8429b7e902e19
[openwrt/staging/stintel.git] /
1 From 172dc9a0d7704051c63407af6b39939c43801a99 Mon Sep 17 00:00:00 2001
2 From: Lei Wei <quic_leiwei@quicinc.com>
3 Date: Fri, 1 Mar 2024 13:36:26 +0800
4 Subject: [PATCH 34/50] net: ethernet: qualcomm: Add PPE port MAC address and
5 EEE functions
6
7 Add PPE port MAC address set and EEE set API functions which
8 will be used by netdev ops and ethtool.
9
10 Change-Id: Id2b3b06ae940b3b6f5227d927316329cdf3caeaa
11 Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
12 ---
13 drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 75 ++++++++++++++++++++
14 drivers/net/ethernet/qualcomm/ppe/ppe_port.h | 3 +
15 drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 29 ++++++++
16 3 files changed, 107 insertions(+)
17
18 diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_port.c b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c
19 index 284ee14b8d03..a9781e1197f7 100644
20 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.c
21 +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c
22 @@ -462,6 +462,81 @@ void ppe_port_get_stats64(struct ppe_port *ppe_port,
23 }
24 }
25
26 +/**
27 + * ppe_port_set_mac_address() - Set PPE port MAC address
28 + * @ppe_port: PPE port
29 + * @addr: MAC address
30 + *
31 + * Description: Set MAC address for the given PPE port.
32 + *
33 + * Return: 0 upon success or a negative error upon failure.
34 + */
35 +int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr)
36 +{
37 + struct ppe_device *ppe_dev = ppe_port->ppe_dev;
38 + int port = ppe_port->port_id;
39 + u32 reg, val;
40 + int ret;
41 +
42 + if (ppe_port->mac_type == PPE_MAC_TYPE_GMAC) {
43 + reg = PPE_PORT_GMAC_ADDR(port);
44 + val = (addr[5] << 8) | addr[4];
45 + ret = regmap_write(ppe_dev->regmap, reg + GMAC_GOL_ADDR0_ADDR, val);
46 + if (ret)
47 + return ret;
48 +
49 + val = (addr[0] << 24) | (addr[1] << 16) |
50 + (addr[2] << 8) | addr[3];
51 + ret = regmap_write(ppe_dev->regmap, reg + GMAC_GOL_ADDR1_ADDR, val);
52 + if (ret)
53 + return ret;
54 + } else {
55 + reg = PPE_PORT_XGMAC_ADDR(port);
56 + val = (addr[5] << 8) | addr[4] | XGMAC_ADDR_EN;
57 + ret = regmap_write(ppe_dev->regmap, reg + XGMAC_ADDR0_H_ADDR, val);
58 + if (ret)
59 + return ret;
60 +
61 + val = (addr[3] << 24) | (addr[2] << 16) |
62 + (addr[1] << 8) | addr[0];
63 + ret = regmap_write(ppe_dev->regmap, reg + XGMAC_ADDR0_L_ADDR, val);
64 + if (ret)
65 + return ret;
66 + }
67 +
68 + return 0;
69 +}
70 +
71 +/**
72 + * ppe_port_set_mac_eee() - Set EEE configuration for PPE port MAC
73 + * @ppe_port: PPE port
74 + * @eee: EEE settings
75 + *
76 + * Description: Set port MAC EEE settings for the given PPE port.
77 + *
78 + * Return: 0 upon success or a negative error upon failure.
79 + */
80 +int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_eee *eee)
81 +{
82 + struct ppe_device *ppe_dev = ppe_port->ppe_dev;
83 + int port = ppe_port->port_id;
84 + u32 val;
85 + int ret;
86 +
87 + ret = regmap_read(ppe_dev->regmap, PPE_LPI_EN_ADDR, &val);
88 + if (ret)
89 + return ret;
90 +
91 + if (eee->tx_lpi_enabled)
92 + val |= PPE_LPI_PORT_EN(port);
93 + else
94 + val &= ~PPE_LPI_PORT_EN(port);
95 +
96 + ret = regmap_write(ppe_dev->regmap, PPE_LPI_EN_ADDR, val);
97 +
98 + return ret;
99 +}
100 +
101 /* PPE port and MAC reset */
102 static int ppe_port_mac_reset(struct ppe_port *ppe_port)
103 {
104 diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_port.h b/drivers/net/ethernet/qualcomm/ppe/ppe_port.h
105 index a524d90e1446..2234c9bfbd9a 100644
106 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.h
107 +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.h
108 @@ -8,6 +8,7 @@
109
110 #include <linux/phylink.h>
111
112 +struct ethtool_eee;
113 struct rtnl_link_stats64;
114
115 /**
116 @@ -86,4 +87,6 @@ void ppe_port_get_strings(struct ppe_port *ppe_port, u32 stringset, u8 *data);
117 void ppe_port_get_ethtool_stats(struct ppe_port *ppe_port, u64 *data);
118 void ppe_port_get_stats64(struct ppe_port *ppe_port,
119 struct rtnl_link_stats64 *s);
120 +int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr);
121 +int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_eee *eee);
122 #endif
123 diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
124 index 2cd5bd9fa446..6e6e469247c8 100644
125 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
126 +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
127 @@ -18,6 +18,16 @@
128 #define PPE_PORT5_SEL_PCS1 BIT(4)
129 #define PPE_PORT_SEL_XGMAC(x) (BIT(8) << ((x) - 1))
130
131 +/* PPE port LPI enable register */
132 +#define PPE_LPI_EN_ADDR 0x400
133 +#define PPE_LPI_PORT1_EN BIT(0)
134 +#define PPE_LPI_PORT2_EN BIT(1)
135 +#define PPE_LPI_PORT3_EN BIT(2)
136 +#define PPE_LPI_PORT4_EN BIT(3)
137 +#define PPE_LPI_PORT5_EN BIT(4)
138 +#define PPE_LPI_PORT6_EN BIT(5)
139 +#define PPE_LPI_PORT_EN(x) (BIT(0) << ((x) - 1))
140 +
141 /* There are 15 BM ports and 4 BM groups supported by PPE,
142 * BM port (0-7) is matched to EDMA port 0, BM port (8-13) is matched
143 * to PPE physical port 1-6, BM port 14 is matched to EIP.
144 @@ -580,6 +590,17 @@
145 #define GMAC_SPEED_100 1
146 #define GMAC_SPEED_1000 2
147
148 +/* GMAC MAC address register */
149 +#define GMAC_GOL_ADDR0_ADDR 0x8
150 +#define GMAC_ADDR_BYTE5 GENMASK(15, 8)
151 +#define GMAC_ADDR_BYTE4 GENMASK(7, 0)
152 +
153 +#define GMAC_GOL_ADDR1_ADDR 0xC
154 +#define GMAC_ADDR_BYTE0 GENMASK(31, 24)
155 +#define GMAC_ADDR_BYTE1 GENMASK(23, 16)
156 +#define GMAC_ADDR_BYTE2 GENMASK(15, 8)
157 +#define GMAC_ADDR_BYTE3 GENMASK(7, 0)
158 +
159 /* GMAC control register */
160 #define GMAC_CTRL_ADDR 0x18
161 #define GMAC_TX_THD_M GENMASK(27, 24)
162 @@ -705,6 +726,14 @@
163 #define XGMAC_RX_FLOW_CTRL_ADDR 0x90
164 #define XGMAC_RXFCEN BIT(0)
165
166 +/* XGMAC MAC address register */
167 +#define XGMAC_ADDR0_H_ADDR 0x300
168 +#define XGMAC_ADDR_EN BIT(31)
169 +#define XGMAC_ADDRH GENMASK(15, 0)
170 +
171 +#define XGMAC_ADDR0_L_ADDR 0x304
172 +#define XGMAC_ADDRL GENMASK(31, 0)
173 +
174 /* XGMAC management counters control register */
175 #define XGMAC_MMC_CTRL_ADDR 0x800
176 #define XGMAC_MCF BIT(3)
177 --
178 2.45.2
179
Staging tree of Stijn Tintel