1 From 0cd5141d1866afb23286fe90cd846441fe7aeb39 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
3 Date: Sat, 27 Mar 2021 14:44:11 +0100
4 Subject: [PATCH] PCI: aardvark: Rewrite IRQ code to chained IRQ handler
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 Rewrite the code to use irq_set_chained_handler_and_data() handler with
10 chained_irq_enter() and chained_irq_exit() processing instead of using
13 advk_pcie_irq_handler() reads IRQ status bits and calls other functions
14 based on which bits are set. These functions then read its own IRQ status
15 bits and calls other aardvark functions based on these bits. Finally
16 generic_handle_domain_irq() with translated linux IRQ numbers are called.
18 Signed-off-by: Pali Rohár <pali@kernel.org>
19 Signed-off-by: Marek Behún <kabel@kernel.org>
21 drivers/pci/controller/pci-aardvark.c | 48 +++++++++++++++------------
22 1 file changed, 26 insertions(+), 22 deletions(-)
24 diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
25 index e68773527171..01dfe70d9c2c 100644
26 --- a/drivers/pci/controller/pci-aardvark.c
27 +++ b/drivers/pci/controller/pci-aardvark.c
28 @@ -275,6 +275,7 @@ struct advk_pcie {
33 struct irq_domain *irq_domain;
34 struct irq_chip irq_chip;
35 raw_spinlock_t irq_lock;
36 @@ -1440,21 +1441,26 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
40 -static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
41 +static void advk_pcie_irq_handler(struct irq_desc *desc)
43 - struct advk_pcie *pcie = arg;
45 + struct advk_pcie *pcie = irq_desc_get_handler_data(desc);
46 + struct irq_chip *chip = irq_desc_get_chip(desc);
47 + u32 val, mask, status;
49 - status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
50 - if (!(status & PCIE_IRQ_CORE_INT))
52 + chained_irq_enter(chip, desc);
54 - advk_pcie_handle_int(pcie);
55 + val = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
56 + mask = advk_readl(pcie, HOST_CTRL_INT_MASK_REG);
57 + status = val & ((~mask) & PCIE_IRQ_ALL_MASK);
59 - /* Clear interrupt */
60 - advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
61 + if (status & PCIE_IRQ_CORE_INT) {
62 + advk_pcie_handle_int(pcie);
65 + /* Clear interrupt */
66 + advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
69 + chained_irq_exit(chip, desc);
72 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)
73 @@ -1521,7 +1527,7 @@ static int advk_pcie_probe(struct platform_device *pdev)
74 struct advk_pcie *pcie;
75 struct pci_host_bridge *bridge;
76 struct resource_entry *entry;
80 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
82 @@ -1609,17 +1615,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
83 if (IS_ERR(pcie->base))
84 return PTR_ERR(pcie->base);
86 - irq = platform_get_irq(pdev, 0);
90 - ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
91 - IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
94 - dev_err(dev, "Failed to register interrupt\n");
97 + pcie->irq = platform_get_irq(pdev, 0);
101 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,
103 @@ -1668,11 +1666,14 @@ static int advk_pcie_probe(struct platform_device *pdev)
107 + irq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie);
109 bridge->sysdata = pcie;
110 bridge->ops = &advk_pcie_ops;
112 ret = pci_host_probe(bridge);
114 + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
115 advk_pcie_remove_msi_irq_domain(pcie);
116 advk_pcie_remove_irq_domain(pcie);
118 @@ -1720,6 +1721,9 @@ static int advk_pcie_remove(struct platform_device *pdev)
119 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
120 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
122 + /* Remove IRQ handler */
123 + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
125 /* Remove IRQ domains */
126 advk_pcie_remove_msi_irq_domain(pcie);
127 advk_pcie_remove_irq_domain(pcie);