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1 From e0d8ea4ed5fa70fd085a54d0b574a044b9407c39 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Thu, 27 Jun 2024 13:04:23 +0200
4 Subject: [PATCH 1/4] clk: en7523: Add reset-controller support for EN7581 SoC
5
6 Introduce reset API support to EN7581 clock driver.
7
8 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
9 Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
10 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
11 Link: https://lore.kernel.org/r/4f735d17e549ea53769bf5a3f50406debb879a44.1719485847.git.lorenzo@kernel.org
12 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
13 ---
14 drivers/clk/clk-en7523.c | 192 ++++++++++++++++++++++++++++++++++++++-
15 1 file changed, 187 insertions(+), 5 deletions(-)
16
17 --- a/drivers/clk/clk-en7523.c
18 +++ b/drivers/clk/clk-en7523.c
19 @@ -5,7 +5,11 @@
20 #include <linux/io.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23 +#include <linux/reset-controller.h>
24 #include <dt-bindings/clock/en7523-clk.h>
25 +#include <dt-bindings/reset/airoha,en7581-reset.h>
26 +
27 +#define RST_NR_PER_BANK 32
28
29 #define REG_PCI_CONTROL 0x88
30 #define REG_PCI_CONTROL_PERSTOUT BIT(29)
31 @@ -40,6 +44,9 @@
32 #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
33 #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
34
35 +#define REG_RST_CTRL2 0x00
36 +#define REG_RST_CTRL1 0x04
37 +
38 struct en_clk_desc {
39 int id;
40 const char *name;
41 @@ -65,8 +72,20 @@ struct en_clk_gate {
42 struct clk_hw hw;
43 };
44
45 +struct en_rst_data {
46 + const u16 *bank_ofs;
47 + const u16 *idx_map;
48 + void __iomem *base;
49 + struct reset_controller_dev rcdev;
50 +};
51 +
52 struct en_clk_soc_data {
53 const struct clk_ops pcie_ops;
54 + struct {
55 + const u16 *bank_ofs;
56 + const u16 *idx_map;
57 + u16 idx_map_nr;
58 + } reset;
59 int (*hw_init)(struct platform_device *pdev, void __iomem *base,
60 void __iomem *np_base);
61 };
62 @@ -173,6 +192,69 @@ static const struct en_clk_desc en7523_b
63 }
64 };
65
66 +static const u16 en7581_rst_ofs[] = {
67 + REG_RST_CTRL2,
68 + REG_RST_CTRL1,
69 +};
70 +
71 +static const u16 en7581_rst_map[] = {
72 + /* RST_CTRL2 */
73 + [EN7581_XPON_PHY_RST] = 0,
74 + [EN7581_CPU_TIMER2_RST] = 2,
75 + [EN7581_HSUART_RST] = 3,
76 + [EN7581_UART4_RST] = 4,
77 + [EN7581_UART5_RST] = 5,
78 + [EN7581_I2C2_RST] = 6,
79 + [EN7581_XSI_MAC_RST] = 7,
80 + [EN7581_XSI_PHY_RST] = 8,
81 + [EN7581_NPU_RST] = 9,
82 + [EN7581_I2S_RST] = 10,
83 + [EN7581_TRNG_RST] = 11,
84 + [EN7581_TRNG_MSTART_RST] = 12,
85 + [EN7581_DUAL_HSI0_RST] = 13,
86 + [EN7581_DUAL_HSI1_RST] = 14,
87 + [EN7581_HSI_RST] = 15,
88 + [EN7581_DUAL_HSI0_MAC_RST] = 16,
89 + [EN7581_DUAL_HSI1_MAC_RST] = 17,
90 + [EN7581_HSI_MAC_RST] = 18,
91 + [EN7581_WDMA_RST] = 19,
92 + [EN7581_WOE0_RST] = 20,
93 + [EN7581_WOE1_RST] = 21,
94 + [EN7581_HSDMA_RST] = 22,
95 + [EN7581_TDMA_RST] = 24,
96 + [EN7581_EMMC_RST] = 25,
97 + [EN7581_SOE_RST] = 26,
98 + [EN7581_PCIE2_RST] = 27,
99 + [EN7581_XFP_MAC_RST] = 28,
100 + [EN7581_USB_HOST_P1_RST] = 29,
101 + [EN7581_USB_HOST_P1_U3_PHY_RST] = 30,
102 + /* RST_CTRL1 */
103 + [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
104 + [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
105 + [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
106 + [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
107 + [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6,
108 + [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8,
109 + [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11,
110 + [EN7581_UART_RST] = RST_NR_PER_BANK + 12,
111 + [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13,
112 + [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14,
113 + [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
114 + [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
115 + [EN7581_SFC_RST] = RST_NR_PER_BANK + 18,
116 + [EN7581_UART2_RST] = RST_NR_PER_BANK + 19,
117 + [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20,
118 + [EN7581_FE_RST] = RST_NR_PER_BANK + 21,
119 + [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
120 + [EN7581_GSW_RST] = RST_NR_PER_BANK + 23,
121 + [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
122 + [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26,
123 + [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27,
124 + [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
125 + [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
126 + [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
127 +};
128 +
129 static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
130 {
131 const struct en_clk_desc *desc = &en7523_base_clks[i];
132 @@ -375,7 +457,7 @@ static int en7581_clk_hw_init(struct pla
133 void __iomem *pb_base;
134 u32 val;
135
136 - pb_base = devm_platform_ioremap_resource(pdev, 2);
137 + pb_base = devm_platform_ioremap_resource(pdev, 3);
138 if (IS_ERR(pb_base))
139 return PTR_ERR(pb_base);
140
141 @@ -428,6 +510,95 @@ static void en7523_register_clocks(struc
142 clk_data->num = EN7523_NUM_CLOCKS;
143 }
144
145 +static int en7523_reset_update(struct reset_controller_dev *rcdev,
146 + unsigned long id, bool assert)
147 +{
148 + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
149 + void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
150 + u32 val;
151 +
152 + val = readl(addr);
153 + if (assert)
154 + val |= BIT(id % RST_NR_PER_BANK);
155 + else
156 + val &= ~BIT(id % RST_NR_PER_BANK);
157 + writel(val, addr);
158 +
159 + return 0;
160 +}
161 +
162 +static int en7523_reset_assert(struct reset_controller_dev *rcdev,
163 + unsigned long id)
164 +{
165 + return en7523_reset_update(rcdev, id, true);
166 +}
167 +
168 +static int en7523_reset_deassert(struct reset_controller_dev *rcdev,
169 + unsigned long id)
170 +{
171 + return en7523_reset_update(rcdev, id, false);
172 +}
173 +
174 +static int en7523_reset_status(struct reset_controller_dev *rcdev,
175 + unsigned long id)
176 +{
177 + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
178 + void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
179 +
180 + return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
181 +}
182 +
183 +static int en7523_reset_xlate(struct reset_controller_dev *rcdev,
184 + const struct of_phandle_args *reset_spec)
185 +{
186 + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
187 +
188 + if (reset_spec->args[0] >= rcdev->nr_resets)
189 + return -EINVAL;
190 +
191 + return rst_data->idx_map[reset_spec->args[0]];
192 +}
193 +
194 +static const struct reset_control_ops en7523_reset_ops = {
195 + .assert = en7523_reset_assert,
196 + .deassert = en7523_reset_deassert,
197 + .status = en7523_reset_status,
198 +};
199 +
200 +static int en7523_reset_register(struct platform_device *pdev,
201 + const struct en_clk_soc_data *soc_data)
202 +{
203 + struct device *dev = &pdev->dev;
204 + struct en_rst_data *rst_data;
205 + void __iomem *base;
206 +
207 + /* no reset lines available */
208 + if (!soc_data->reset.idx_map_nr)
209 + return 0;
210 +
211 + base = devm_platform_ioremap_resource(pdev, 2);
212 + if (IS_ERR(base))
213 + return PTR_ERR(base);
214 +
215 + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
216 + if (!rst_data)
217 + return -ENOMEM;
218 +
219 + rst_data->bank_ofs = soc_data->reset.bank_ofs;
220 + rst_data->idx_map = soc_data->reset.idx_map;
221 + rst_data->base = base;
222 +
223 + rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;
224 + rst_data->rcdev.of_xlate = en7523_reset_xlate;
225 + rst_data->rcdev.ops = &en7523_reset_ops;
226 + rst_data->rcdev.of_node = dev->of_node;
227 + rst_data->rcdev.of_reset_n_cells = 1;
228 + rst_data->rcdev.owner = THIS_MODULE;
229 + rst_data->rcdev.dev = dev;
230 +
231 + return devm_reset_controller_register(dev, &rst_data->rcdev);
232 +}
233 +
234 static int en7523_clk_probe(struct platform_device *pdev)
235 {
236 struct device_node *node = pdev->dev.of_node;
237 @@ -461,11 +632,17 @@ static int en7523_clk_probe(struct platf
238
239 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
240 if (r)
241 - dev_err(&pdev->dev,
242 - "could not register clock provider: %s: %d\n",
243 - pdev->name, r);
244 + return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",
245 + pdev->name);
246 +
247 + r = en7523_reset_register(pdev, soc_data);
248 + if (r) {
249 + of_clk_del_provider(node);
250 + return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",
251 + pdev->name);
252 + }
253
254 - return r;
255 + return 0;
256 }
257
258 static const struct en_clk_soc_data en7523_data = {
259 @@ -484,6 +661,11 @@ static const struct en_clk_soc_data en75
260 .unprepare = en7581_pci_unprepare,
261 .disable = en7581_pci_disable,
262 },
263 + .reset = {
264 + .bank_ofs = en7581_rst_ofs,
265 + .idx_map = en7581_rst_map,
266 + .idx_map_nr = ARRAY_SIZE(en7581_rst_map),
267 + },
268 .hw_init = en7581_clk_hw_init,
269 };
270
Staging tree of David Bauer