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1 From patchwork Mon Dec 27 18:31:43 2021
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
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5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
6 X-Patchwork-Id: 12699994
7 X-Patchwork-Delegate: kuba@kernel.org
8 Return-Path: <netdev-owner@kernel.org>
9 Date: Mon, 27 Dec 2021 18:31:43 +0000
10 From: Daniel Golle <daniel@makrotopia.org>
11 To: linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
12 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
13 Cc: Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
14 Sean Wang <sean.wang@mediatek.com>,
15 Mark Lee <Mark-MC.Lee@mediatek.com>,
16 "David S. Miller" <davem@davemloft.net>,
17 Jakub Kicinski <kuba@kernel.org>,
18 Matthias Brugger <matthias.bgg@gmail.com>,
19 Russell King <linux@armlinux.org.uk>,
20 Andrew Lunn <andrew@lunn.ch>
21 Subject: [PATCH v5 2/2] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
22 access
23 Message-ID: <YcoGj4Rj5mJlXz4D@makrotopia.org>
24 References: <YcnoAscVe+2YILT8@shell.armlinux.org.uk>
25 <YcnlMtninjjjPhjI@makrotopia.org>
26 MIME-Version: 1.0
27 Content-Disposition: inline
28 In-Reply-To: <YcnoAscVe+2YILT8@shell.armlinux.org.uk>
29 <YcnlMtninjjjPhjI@makrotopia.org>
30 Precedence: bulk
31 List-ID: <netdev.vger.kernel.org>
32 X-Mailing-List: netdev@vger.kernel.org
33 X-Patchwork-Delegate: kuba@kernel.org
34
35 Implement read and write access to IEEE 802.3 Clause 45 Ethernet
36 phy registers.
37 Tested on the Ubiquiti UniFi 6 LR access point featuring
38 MediaTek MT7622BV WiSoC with Aquantia AQR112C.
39
40 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
41 ---
42 v5: unchanged
43 v4: clean-up return values and types, split into two commits
44 v3: return -1 instead of 0xffff on error in _mtk_mdio_write
45 v2: use MII_DEVADDR_C45_SHIFT and MII_REGADDR_C45_MASK to extract
46 device id and register address. Unify read and write functions to
47 have identical types and parameter names where possible as we are
48 anyway already replacing both function bodies.
49
50
51 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 60 +++++++++++++++++----
52 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 ++
53 2 files changed, 53 insertions(+), 10 deletions(-)
54
55 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
56 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
57 @@ -103,10 +103,30 @@ static int _mtk_mdio_write(struct mtk_et
58
59 write_data &= 0xffff;
60
61 - mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
62 - (phy_reg << PHY_IAC_REG_SHIFT) |
63 - (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
64 - MTK_PHY_IAC);
65 + if (phy_reg & MII_ADDR_C45) {
66 + u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
67 + u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
68 +
69 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
70 + (phy_addr << PHY_IAC_ADDR_SHIFT) |
71 + (dev_num << PHY_IAC_REG_SHIFT) |
72 + reg,
73 + MTK_PHY_IAC);
74 +
75 + if (mtk_mdio_busy_wait(eth))
76 + return -EBUSY;
77 +
78 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE |
79 + (phy_addr << PHY_IAC_ADDR_SHIFT) |
80 + (dev_num << PHY_IAC_REG_SHIFT) |
81 + write_data,
82 + MTK_PHY_IAC);
83 + } else {
84 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
85 + (phy_reg << PHY_IAC_REG_SHIFT) |
86 + (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
87 + MTK_PHY_IAC);
88 + }
89
90 if (mtk_mdio_busy_wait(eth))
91 return -EBUSY;
92 @@ -114,17 +134,36 @@ static int _mtk_mdio_write(struct mtk_et
93 return 0;
94 }
95
96 -static int _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
97 +static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
98 {
99 - u32 d;
100 + int d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return -EBUSY;
104
105 - mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 - (phy_reg << PHY_IAC_REG_SHIFT) |
107 - (phy_addr << PHY_IAC_ADDR_SHIFT),
108 - MTK_PHY_IAC);
109 + if (phy_reg & MII_ADDR_C45) {
110 + u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
111 + u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
112 +
113 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
114 + (phy_addr << PHY_IAC_ADDR_SHIFT) |
115 + (dev_num << PHY_IAC_REG_SHIFT) |
116 + reg,
117 + MTK_PHY_IAC);
118 +
119 + if (mtk_mdio_busy_wait(eth))
120 + return -EBUSY;
121 +
122 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 |
123 + (phy_addr << PHY_IAC_ADDR_SHIFT) |
124 + (dev_num << PHY_IAC_REG_SHIFT),
125 + MTK_PHY_IAC);
126 + } else {
127 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
128 + (phy_reg << PHY_IAC_REG_SHIFT) |
129 + (phy_addr << PHY_IAC_ADDR_SHIFT),
130 + MTK_PHY_IAC);
131 + }
132
133 if (mtk_mdio_busy_wait(eth))
134 return -EBUSY;
135 @@ -584,6 +623,7 @@ static int mtk_mdio_init(struct mtk_eth
136 eth->mii_bus->name = "mdio";
137 eth->mii_bus->read = mtk_mdio_read;
138 eth->mii_bus->write = mtk_mdio_write;
139 + eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
140 eth->mii_bus->priv = eth;
141 eth->mii_bus->parent = eth->dev;
142
143 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
144 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
145 @@ -340,9 +340,12 @@
146 /* PHY Indirect Access Control registers */
147 #define MTK_PHY_IAC 0x10004
148 #define PHY_IAC_ACCESS BIT(31)
149 +#define PHY_IAC_SET_ADDR 0
150 #define PHY_IAC_READ BIT(19)
151 +#define PHY_IAC_READ_C45 (BIT(18) | BIT(19))
152 #define PHY_IAC_WRITE BIT(18)
153 #define PHY_IAC_START BIT(16)
154 +#define PHY_IAC_START_C45 0
155 #define PHY_IAC_ADDR_SHIFT 20
156 #define PHY_IAC_REG_SHIFT 25
157 #define PHY_IAC_TIMEOUT HZ
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