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1 From c3f16eeaa68f3be291dd62efadeb733d6d40279a Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Tue, 18 Feb 2020 09:13:00 +0800
4 Subject: [PATCH] Revert "PCI: mobiveil: Fix csr_read()/write() build issue"
5
6 This reverts commit 1865d6440fb63ad979d7034b2d7c94937bfd2200.
7
8 PCI: mobiveil: Fix csr_read()/write() build issue
9
10 [ Upstream commit 4906c05b87d44c19b225935e24d62e4480ca556d ]
11 ---
12 drivers/pci/controller/pcie-mobiveil.c | 119 ++++++++++++++++-----------------
13 1 file changed, 57 insertions(+), 62 deletions(-)
14
15 --- a/drivers/pci/controller/pcie-mobiveil.c
16 +++ b/drivers/pci/controller/pcie-mobiveil.c
17 @@ -235,7 +235,7 @@ static int mobiveil_pcie_write(void __io
18 return PCIBIOS_SUCCESSFUL;
19 }
20
21 -static u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
22 +static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
23 {
24 void *addr;
25 u32 val;
26 @@ -250,8 +250,7 @@ static u32 mobiveil_csr_read(struct mobi
27 return val;
28 }
29
30 -static void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
31 - size_t size)
32 +static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
33 {
34 void *addr;
35 int ret;
36 @@ -263,19 +262,19 @@ static void mobiveil_csr_write(struct mo
37 dev_err(&pcie->pdev->dev, "write CSR address failed\n");
38 }
39
40 -static u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
41 +static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
42 {
43 - return mobiveil_csr_read(pcie, off, 0x4);
44 + return csr_read(pcie, off, 0x4);
45 }
46
47 -static void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
48 +static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
49 {
50 - mobiveil_csr_write(pcie, val, off, 0x4);
51 + csr_write(pcie, val, off, 0x4);
52 }
53
54 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
55 {
56 - return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
57 + return (csr_readl(pcie, LTSSM_STATUS) &
58 LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
59 }
60
61 @@ -324,7 +323,7 @@ static void __iomem *mobiveil_pcie_map_b
62 PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
63 PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
64
65 - mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
66 + csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
67
68 return pcie->config_axi_slave_base + where;
69 }
70 @@ -354,14 +353,13 @@ static void mobiveil_pcie_isr(struct irq
71 chained_irq_enter(chip, desc);
72
73 /* read INTx status */
74 - val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
75 - mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
76 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
77 + mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
78 intr_status = val & mask;
79
80 /* Handle INTx */
81 if (intr_status & PAB_INTP_INTX_MASK) {
82 - shifted_status = mobiveil_csr_readl(pcie,
83 - PAB_INTP_AMBA_MISC_STAT);
84 + shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
85 shifted_status &= PAB_INTP_INTX_MASK;
86 shifted_status >>= PAB_INTX_START;
87 do {
88 @@ -375,13 +373,12 @@ static void mobiveil_pcie_isr(struct irq
89 bit);
90
91 /* clear interrupt handled */
92 - mobiveil_csr_writel(pcie,
93 - 1 << (PAB_INTX_START + bit),
94 - PAB_INTP_AMBA_MISC_STAT);
95 + csr_writel(pcie, 1 << (PAB_INTX_START + bit),
96 + PAB_INTP_AMBA_MISC_STAT);
97 }
98
99 - shifted_status = mobiveil_csr_readl(pcie,
100 - PAB_INTP_AMBA_MISC_STAT);
101 + shifted_status = csr_readl(pcie,
102 + PAB_INTP_AMBA_MISC_STAT);
103 shifted_status &= PAB_INTP_INTX_MASK;
104 shifted_status >>= PAB_INTX_START;
105 } while (shifted_status != 0);
106 @@ -416,7 +413,7 @@ static void mobiveil_pcie_isr(struct irq
107 }
108
109 /* Clear the interrupt status */
110 - mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
111 + csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
112 chained_irq_exit(chip, desc);
113 }
114
115 @@ -477,24 +474,24 @@ static void program_ib_windows(struct mo
116 return;
117 }
118
119 - value = mobiveil_csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
120 + value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
121 value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
122 value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
123 (lower_32_bits(size64) & WIN_SIZE_MASK);
124 - mobiveil_csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
125 + csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
126
127 - mobiveil_csr_writel(pcie, upper_32_bits(size64),
128 - PAB_EXT_PEX_AMAP_SIZEN(win_num));
129 + csr_writel(pcie, upper_32_bits(size64),
130 + PAB_EXT_PEX_AMAP_SIZEN(win_num));
131
132 - mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr),
133 - PAB_PEX_AMAP_AXI_WIN(win_num));
134 - mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
135 - PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
136 -
137 - mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
138 - PAB_PEX_AMAP_PEX_WIN_L(win_num));
139 - mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
140 - PAB_PEX_AMAP_PEX_WIN_H(win_num));
141 + csr_writel(pcie, lower_32_bits(cpu_addr),
142 + PAB_PEX_AMAP_AXI_WIN(win_num));
143 + csr_writel(pcie, upper_32_bits(cpu_addr),
144 + PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
145 +
146 + csr_writel(pcie, lower_32_bits(pci_addr),
147 + PAB_PEX_AMAP_PEX_WIN_L(win_num));
148 + csr_writel(pcie, upper_32_bits(pci_addr),
149 + PAB_PEX_AMAP_PEX_WIN_H(win_num));
150
151 pcie->ib_wins_configured++;
152 }
153 @@ -518,29 +515,27 @@ static void program_ob_windows(struct mo
154 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
155 * to 4 KB in PAB_AXI_AMAP_CTRL register
156 */
157 - value = mobiveil_csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
158 + value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
159 value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
160 value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
161 (lower_32_bits(size64) & WIN_SIZE_MASK);
162 - mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
163 + csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
164
165 - mobiveil_csr_writel(pcie, upper_32_bits(size64),
166 - PAB_EXT_AXI_AMAP_SIZE(win_num));
167 + csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
168
169 /*
170 * program AXI window base with appropriate value in
171 * PAB_AXI_AMAP_AXI_WIN0 register
172 */
173 - mobiveil_csr_writel(pcie,
174 - lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
175 - PAB_AXI_AMAP_AXI_WIN(win_num));
176 - mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
177 - PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
178 -
179 - mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
180 - PAB_AXI_AMAP_PEX_WIN_L(win_num));
181 - mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
182 - PAB_AXI_AMAP_PEX_WIN_H(win_num));
183 + csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
184 + PAB_AXI_AMAP_AXI_WIN(win_num));
185 + csr_writel(pcie, upper_32_bits(cpu_addr),
186 + PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
187 +
188 + csr_writel(pcie, lower_32_bits(pci_addr),
189 + PAB_AXI_AMAP_PEX_WIN_L(win_num));
190 + csr_writel(pcie, upper_32_bits(pci_addr),
191 + PAB_AXI_AMAP_PEX_WIN_H(win_num));
192
193 pcie->ob_wins_configured++;
194 }
195 @@ -584,42 +579,42 @@ static int mobiveil_host_init(struct mob
196 struct resource_entry *win;
197
198 /* setup bus numbers */
199 - value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
200 + value = csr_readl(pcie, PCI_PRIMARY_BUS);
201 value &= 0xff000000;
202 value |= 0x00ff0100;
203 - mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
204 + csr_writel(pcie, value, PCI_PRIMARY_BUS);
205
206 /*
207 * program Bus Master Enable Bit in Command Register in PAB Config
208 * Space
209 */
210 - value = mobiveil_csr_readl(pcie, PCI_COMMAND);
211 + value = csr_readl(pcie, PCI_COMMAND);
212 value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
213 - mobiveil_csr_writel(pcie, value, PCI_COMMAND);
214 + csr_writel(pcie, value, PCI_COMMAND);
215
216 /*
217 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
218 * register
219 */
220 - pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
221 + pab_ctrl = csr_readl(pcie, PAB_CTRL);
222 pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
223 - mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
224 + csr_writel(pcie, pab_ctrl, PAB_CTRL);
225
226 - mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
227 - PAB_INTP_AMBA_MISC_ENB);
228 + csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
229 + PAB_INTP_AMBA_MISC_ENB);
230
231 /*
232 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
233 * PAB_AXI_PIO_CTRL Register
234 */
235 - value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
236 + value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
237 value |= APIO_EN_MASK;
238 - mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
239 + csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
240
241 /* Enable PCIe PIO master */
242 - value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
243 + value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
244 value |= 1 << PIO_ENABLE_SHIFT;
245 - mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
246 + csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
247
248 /*
249 * we'll program one outbound window for config reads and
250 @@ -652,10 +647,10 @@ static int mobiveil_host_init(struct mob
251 }
252
253 /* fixup for PCIe class register */
254 - value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
255 + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
256 value &= 0xff;
257 value |= (PCI_CLASS_BRIDGE_PCI << 16);
258 - mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
259 + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
260
261 /* setup MSI hardware registers */
262 mobiveil_pcie_enable_msi(pcie);
263 @@ -673,9 +668,9 @@ static void mobiveil_mask_intx_irq(struc
264 pcie = irq_desc_get_chip_data(desc);
265 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
266 raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
267 - shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
268 + shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
269 shifted_val &= ~mask;
270 - mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
271 + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
272 raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
273 }
274
275 @@ -689,9 +684,9 @@ static void mobiveil_unmask_intx_irq(str
276 pcie = irq_desc_get_chip_data(desc);
277 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
278 raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
279 - shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
280 + shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
281 shifted_val |= mask;
282 - mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
283 + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
284 raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
285 }
286
Staging tree of Piotr Dymacz