git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From fd5ec7c0a9f7167baf377a4bbae72eda391df996 Mon Sep 17 00:00:00 2001
   2 From: Luo Jie <quic_luoj@quicinc.com>
   3 Date: Wed, 8 Nov 2023 16:18:02 +0800
   4 Subject: [PATCH 03/50] net: phy: qca808x: Add config_init function for QCA8084
   5
   6 1. The ADC of QCA8084 PHY must be configured as edge inverted
   7 and falling whenever it is initialized or reset. In addition,
   8 the default MSE (Mean square error) threshold value is adjusted,
   9 which comes into play during link partner detection to detect
  10 the valid link signal.
  11
  12 2. Add the possible interface modes.
  13    When QCA8084 works on the interface mode SGMII or 2500BASE-X, the
  14    interface mode can be switched according to the PHY link speed.
  15
  16    When QCA8084 works on the 10G-QXGMII mode, which will be the only
  17    possible interface mode.
  18
  19 Change-Id: I832c0d0b069e95cc411a8a7b680a5f60e1d6041a
  20 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  21 ---
  22  drivers/net/phy/qcom/qca808x.c | 38 ++++++++++++++++++++++++++++++++++
  23  1 file changed, 38 insertions(+)
  24
  25 diff --git a/drivers/net/phy/qcom/qca808x.c b/drivers/net/phy/qcom/qca808x.c
  26 index be46d16ca09f..c88fa59d4029 100644
  27 --- a/drivers/net/phy/qcom/qca808x.c
  28 +++ b/drivers/net/phy/qcom/qca808x.c
  29 @@ -94,6 +94,15 @@
  30  #define QCA8084_MMD3_CDT_NEAR_CTRL             0x807f
  31  #define QCA8084_CDT_NEAR_BYPASS                        BIT(15)
  32
  33 +/* QCA8084 ADC clock edge */
  34 +#define QCA8084_ADC_CLK_SEL                    0x8b80
  35 +#define QCA8084_ADC_CLK_SEL_ACLK               GENMASK(7, 4)
  36 +#define QCA8084_ADC_CLK_SEL_ACLK_FALL          0xf
  37 +#define QCA8084_ADC_CLK_SEL_ACLK_RISE          0x0
  38 +
  39 +#define QCA8084_MSE_THRESHOLD                  0x800a
  40 +#define QCA8084_MSE_THRESHOLD_2P5G_VAL         0x51c6
  41 +
  42  MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
  43  MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
  44  MODULE_LICENSE("GPL");
  45 @@ -660,6 +669,34 @@ static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
  46                               active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
  47  }
  48
  49 +static int qca8084_config_init(struct phy_device *phydev)
  50 +{
  51 +       int ret;
  52 +
  53 +       if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
  54 +               __set_bit(PHY_INTERFACE_MODE_10G_QXGMII,
  55 +                         phydev->possible_interfaces);
  56 +       else
  57 +               qca808x_fill_possible_interfaces(phydev);
  58 +
  59 +       /* Configure the ADC to convert the signal using falling edge
  60 +        * instead of the default rising edge.
  61 +        */
  62 +       ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL,
  63 +                                   QCA8084_ADC_CLK_SEL_ACLK,
  64 +                                   FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK,
  65 +                                              QCA8084_ADC_CLK_SEL_ACLK_FALL));
  66 +       if (ret < 0)
  67 +               return ret;
  68 +
  69 +       /* Adjust MSE threshold value to avoid link issue with
  70 +        * some link partner.
  71 +        */
  72 +       return phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
  73 +                            QCA8084_MSE_THRESHOLD,
  74 +                            QCA8084_MSE_THRESHOLD_2P5G_VAL);
  75 +}
  76 +
  77  static struct phy_driver qca808x_driver[] = {
  78  {
  79         /* Qualcomm QCA8081 */
  80 @@ -708,6 +745,7 @@ static struct phy_driver qca808x_driver[] = {
  81         .soft_reset             = qca808x_soft_reset,
  82         .cable_test_start       = qca808x_cable_test_start,
  83         .cable_test_get_status  = qca808x_cable_test_get_status,
  84 +       .config_init            = qca8084_config_init,
  85  }, };
  86
  87  module_phy_driver(qca808x_driver);
  88 --
  89 2.45.2
  90