projects / openwrt / staging / 981213.git / blob
? search:


f491d2fd80cf353b572b148e81ec818b3c892a07
[openwrt/staging/981213.git] /
1 From: Sujuan Chen <sujuan.chen@mediatek.com>
2 Date: Mon, 18 Sep 2023 12:29:18 +0200
3 Subject: [PATCH] net: ethernet: mtk_wed: debugfs: add WED 3.0 debugfs entries
4
5 Introduce WED3.0 debugfs entries useful for debugging.
6
7 Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
8 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
9 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
10 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
11 ---
12
13 --- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
14 +++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
15 @@ -11,6 +11,7 @@ struct reg_dump {
16 u16 offset;
17 u8 type;
18 u8 base;
19 + u32 mask;
20 };
21
22 enum {
23 @@ -25,6 +26,8 @@ enum {
24
25 #define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }
26 #define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ }
27 +#define DUMP_REG_MASK(_reg, _mask) \
28 + { #_mask, MTK_##_reg, DUMP_TYPE_WED, 0, MTK_##_mask }
29 #define DUMP_RING(_prefix, _base, ...) \
30 { _prefix " BASE", _base, __VA_ARGS__ }, \
31 { _prefix " CNT", _base + 0x4, __VA_ARGS__ }, \
32 @@ -32,6 +35,7 @@ enum {
33 { _prefix " DIDX", _base + 0xc, __VA_ARGS__ }
34
35 #define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)
36 +#define DUMP_WED_MASK(_reg, _mask) DUMP_REG_MASK(_reg, _mask)
37 #define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED)
38
39 #define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)
40 @@ -212,12 +216,58 @@ wed_rxinfo_show(struct seq_file *s, void
41 DUMP_WED(WED_RTQM_Q2B_MIB),
42 DUMP_WED(WED_RTQM_PFDBK_MIB),
43 };
44 + static const struct reg_dump regs_wed_v3[] = {
45 + DUMP_STR("WED RX RRO DATA"),
46 + DUMP_WED_RING(WED_RRO_RX_D_RX(0)),
47 + DUMP_WED_RING(WED_RRO_RX_D_RX(1)),
48 +
49 + DUMP_STR("WED RX MSDU PAGE"),
50 + DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(0)),
51 + DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(1)),
52 + DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(2)),
53 +
54 + DUMP_STR("WED RX IND CMD"),
55 + DUMP_WED(WED_IND_CMD_RX_CTRL1),
56 + DUMP_WED_MASK(WED_IND_CMD_RX_CTRL2, WED_IND_CMD_MAX_CNT),
57 + DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_PROC_IDX),
58 + DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_DMA_IDX),
59 + DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_MAGIC_CNT),
60 + DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_MAGIC_CNT),
61 + DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0,
62 + WED_IND_CMD_PREFETCH_FREE_CNT),
63 + DUMP_WED_MASK(WED_RRO_CFG1, WED_RRO_CFG1_PARTICL_SE_ID),
64 +
65 + DUMP_STR("WED ADDR ELEM"),
66 + DUMP_WED(WED_ADDR_ELEM_CFG0),
67 + DUMP_WED_MASK(WED_ADDR_ELEM_CFG1,
68 + WED_ADDR_ELEM_PREFETCH_FREE_CNT),
69 +
70 + DUMP_STR("WED Route QM"),
71 + DUMP_WED(WED_RTQM_ENQ_I2Q_DMAD_CNT),
72 + DUMP_WED(WED_RTQM_ENQ_I2N_DMAD_CNT),
73 + DUMP_WED(WED_RTQM_ENQ_I2Q_PKT_CNT),
74 + DUMP_WED(WED_RTQM_ENQ_I2N_PKT_CNT),
75 + DUMP_WED(WED_RTQM_ENQ_USED_ENTRY_CNT),
76 + DUMP_WED(WED_RTQM_ENQ_ERR_CNT),
77 +
78 + DUMP_WED(WED_RTQM_DEQ_DMAD_CNT),
79 + DUMP_WED(WED_RTQM_DEQ_Q2I_DMAD_CNT),
80 + DUMP_WED(WED_RTQM_DEQ_PKT_CNT),
81 + DUMP_WED(WED_RTQM_DEQ_Q2I_PKT_CNT),
82 + DUMP_WED(WED_RTQM_DEQ_USED_PFDBK_CNT),
83 + DUMP_WED(WED_RTQM_DEQ_ERR_CNT),
84 + };
85 struct mtk_wed_hw *hw = s->private;
86 struct mtk_wed_device *dev = hw->wed_dev;
87
88 if (dev) {
89 dump_wed_regs(s, dev, regs_common, ARRAY_SIZE(regs_common));
90 - dump_wed_regs(s, dev, regs_wed_v2, ARRAY_SIZE(regs_wed_v2));
91 + if (mtk_wed_is_v2(hw))
92 + dump_wed_regs(s, dev,
93 + regs_wed_v2, ARRAY_SIZE(regs_wed_v2));
94 + else
95 + dump_wed_regs(s, dev,
96 + regs_wed_v3, ARRAY_SIZE(regs_wed_v3));
97 }
98
99 return 0;
100 @@ -225,6 +275,314 @@ wed_rxinfo_show(struct seq_file *s, void
101 DEFINE_SHOW_ATTRIBUTE(wed_rxinfo);
102
103 static int
104 +wed_amsdu_show(struct seq_file *s, void *data)
105 +{
106 + static const struct reg_dump regs[] = {
107 + DUMP_STR("WED AMDSU INFO"),
108 + DUMP_WED(WED_MON_AMSDU_FIFO_DMAD),
109 +
110 + DUMP_STR("WED AMDSU ENG0 INFO"),
111 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(0)),
112 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(0)),
113 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(0)),
114 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(0)),
115 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(0)),
116 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(0),
117 + WED_AMSDU_ENG_MAX_PL_CNT),
118 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(0),
119 + WED_AMSDU_ENG_MAX_QGPP_CNT),
120 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
121 + WED_AMSDU_ENG_CUR_ENTRY),
122 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
123 + WED_AMSDU_ENG_MAX_BUF_MERGED),
124 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
125 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
126 +
127 + DUMP_STR("WED AMDSU ENG1 INFO"),
128 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(1)),
129 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(1)),
130 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(1)),
131 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(1)),
132 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(1)),
133 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(1),
134 + WED_AMSDU_ENG_MAX_PL_CNT),
135 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(1),
136 + WED_AMSDU_ENG_MAX_QGPP_CNT),
137 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(1),
138 + WED_AMSDU_ENG_CUR_ENTRY),
139 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
140 + WED_AMSDU_ENG_MAX_BUF_MERGED),
141 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
142 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
143 +
144 + DUMP_STR("WED AMDSU ENG2 INFO"),
145 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(2)),
146 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(2)),
147 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(2)),
148 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(2)),
149 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(2)),
150 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(2),
151 + WED_AMSDU_ENG_MAX_PL_CNT),
152 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(2),
153 + WED_AMSDU_ENG_MAX_QGPP_CNT),
154 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
155 + WED_AMSDU_ENG_CUR_ENTRY),
156 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
157 + WED_AMSDU_ENG_MAX_BUF_MERGED),
158 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
159 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
160 +
161 + DUMP_STR("WED AMDSU ENG3 INFO"),
162 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(3)),
163 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(3)),
164 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(3)),
165 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(3)),
166 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(3)),
167 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(3),
168 + WED_AMSDU_ENG_MAX_PL_CNT),
169 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(3),
170 + WED_AMSDU_ENG_MAX_QGPP_CNT),
171 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
172 + WED_AMSDU_ENG_CUR_ENTRY),
173 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
174 + WED_AMSDU_ENG_MAX_BUF_MERGED),
175 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
176 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
177 +
178 + DUMP_STR("WED AMDSU ENG4 INFO"),
179 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(4)),
180 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(4)),
181 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(4)),
182 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(4)),
183 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(4)),
184 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(4),
185 + WED_AMSDU_ENG_MAX_PL_CNT),
186 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(4),
187 + WED_AMSDU_ENG_MAX_QGPP_CNT),
188 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
189 + WED_AMSDU_ENG_CUR_ENTRY),
190 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
191 + WED_AMSDU_ENG_MAX_BUF_MERGED),
192 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
193 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
194 +
195 + DUMP_STR("WED AMDSU ENG5 INFO"),
196 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(5)),
197 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(5)),
198 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(5)),
199 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(5)),
200 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(5)),
201 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(5),
202 + WED_AMSDU_ENG_MAX_PL_CNT),
203 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(5),
204 + WED_AMSDU_ENG_MAX_QGPP_CNT),
205 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
206 + WED_AMSDU_ENG_CUR_ENTRY),
207 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
208 + WED_AMSDU_ENG_MAX_BUF_MERGED),
209 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
210 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
211 +
212 + DUMP_STR("WED AMDSU ENG6 INFO"),
213 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(6)),
214 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(6)),
215 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(6)),
216 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(6)),
217 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(6)),
218 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(6),
219 + WED_AMSDU_ENG_MAX_PL_CNT),
220 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(6),
221 + WED_AMSDU_ENG_MAX_QGPP_CNT),
222 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
223 + WED_AMSDU_ENG_CUR_ENTRY),
224 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
225 + WED_AMSDU_ENG_MAX_BUF_MERGED),
226 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
227 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
228 +
229 + DUMP_STR("WED AMDSU ENG7 INFO"),
230 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(7)),
231 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(7)),
232 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(7)),
233 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(7)),
234 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(7)),
235 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(7),
236 + WED_AMSDU_ENG_MAX_PL_CNT),
237 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(7),
238 + WED_AMSDU_ENG_MAX_QGPP_CNT),
239 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(7),
240 + WED_AMSDU_ENG_CUR_ENTRY),
241 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(7),
242 + WED_AMSDU_ENG_MAX_BUF_MERGED),
243 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
244 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
245 +
246 + DUMP_STR("WED AMDSU ENG8 INFO"),
247 + DUMP_WED(WED_MON_AMSDU_ENG_DMAD(8)),
248 + DUMP_WED(WED_MON_AMSDU_ENG_QFPL(8)),
249 + DUMP_WED(WED_MON_AMSDU_ENG_QENI(8)),
250 + DUMP_WED(WED_MON_AMSDU_ENG_QENO(8)),
251 + DUMP_WED(WED_MON_AMSDU_ENG_MERG(8)),
252 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(8),
253 + WED_AMSDU_ENG_MAX_PL_CNT),
254 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(8),
255 + WED_AMSDU_ENG_MAX_QGPP_CNT),
256 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
257 + WED_AMSDU_ENG_CUR_ENTRY),
258 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
259 + WED_AMSDU_ENG_MAX_BUF_MERGED),
260 + DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
261 + WED_AMSDU_ENG_MAX_MSDU_MERGED),
262 +
263 + DUMP_STR("WED QMEM INFO"),
264 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(0), WED_AMSDU_QMEM_FQ_CNT),
265 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(0), WED_AMSDU_QMEM_SP_QCNT),
266 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(1), WED_AMSDU_QMEM_TID0_QCNT),
267 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(1), WED_AMSDU_QMEM_TID1_QCNT),
268 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(2), WED_AMSDU_QMEM_TID2_QCNT),
269 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(2), WED_AMSDU_QMEM_TID3_QCNT),
270 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(3), WED_AMSDU_QMEM_TID4_QCNT),
271 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(3), WED_AMSDU_QMEM_TID5_QCNT),
272 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(4), WED_AMSDU_QMEM_TID6_QCNT),
273 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(4), WED_AMSDU_QMEM_TID7_QCNT),
274 +
275 + DUMP_STR("WED QMEM HEAD INFO"),
276 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(0), WED_AMSDU_QMEM_FQ_HEAD),
277 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(0), WED_AMSDU_QMEM_SP_QHEAD),
278 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(1), WED_AMSDU_QMEM_TID0_QHEAD),
279 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(1), WED_AMSDU_QMEM_TID1_QHEAD),
280 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(2), WED_AMSDU_QMEM_TID2_QHEAD),
281 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(2), WED_AMSDU_QMEM_TID3_QHEAD),
282 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(3), WED_AMSDU_QMEM_TID4_QHEAD),
283 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(3), WED_AMSDU_QMEM_TID5_QHEAD),
284 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(4), WED_AMSDU_QMEM_TID6_QHEAD),
285 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(4), WED_AMSDU_QMEM_TID7_QHEAD),
286 +
287 + DUMP_STR("WED QMEM TAIL INFO"),
288 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(5), WED_AMSDU_QMEM_FQ_TAIL),
289 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(5), WED_AMSDU_QMEM_SP_QTAIL),
290 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(6), WED_AMSDU_QMEM_TID0_QTAIL),
291 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(6), WED_AMSDU_QMEM_TID1_QTAIL),
292 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(7), WED_AMSDU_QMEM_TID2_QTAIL),
293 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(7), WED_AMSDU_QMEM_TID3_QTAIL),
294 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(8), WED_AMSDU_QMEM_TID4_QTAIL),
295 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(8), WED_AMSDU_QMEM_TID5_QTAIL),
296 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(9), WED_AMSDU_QMEM_TID6_QTAIL),
297 + DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(9), WED_AMSDU_QMEM_TID7_QTAIL),
298 +
299 + DUMP_STR("WED HIFTXD MSDU INFO"),
300 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(1)),
301 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(2)),
302 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(3)),
303 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(4)),
304 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(5)),
305 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(6)),
306 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(7)),
307 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(8)),
308 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(9)),
309 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(10)),
310 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(11)),
311 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(12)),
312 + DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(13)),
313 + };
314 + struct mtk_wed_hw *hw = s->private;
315 + struct mtk_wed_device *dev = hw->wed_dev;
316 +
317 + if (dev)
318 + dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
319 +
320 + return 0;
321 +}
322 +DEFINE_SHOW_ATTRIBUTE(wed_amsdu);
323 +
324 +static int
325 +wed_rtqm_show(struct seq_file *s, void *data)
326 +{
327 + static const struct reg_dump regs[] = {
328 + DUMP_STR("WED Route QM IGRS0(N2H + Recycle)"),
329 + DUMP_WED(WED_RTQM_IGRS0_I2HW_DMAD_CNT),
330 + DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(0)),
331 + DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(1)),
332 + DUMP_WED(WED_RTQM_IGRS0_I2HW_PKT_CNT),
333 + DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
334 + DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
335 + DUMP_WED(WED_RTQM_IGRS0_FDROP_CNT),
336 +
337 + DUMP_STR("WED Route QM IGRS1(Legacy)"),
338 + DUMP_WED(WED_RTQM_IGRS1_I2HW_DMAD_CNT),
339 + DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(0)),
340 + DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(1)),
341 + DUMP_WED(WED_RTQM_IGRS1_I2HW_PKT_CNT),
342 + DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(0)),
343 + DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(1)),
344 + DUMP_WED(WED_RTQM_IGRS1_FDROP_CNT),
345 +
346 + DUMP_STR("WED Route QM IGRS2(RRO3.0)"),
347 + DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
348 + DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(0)),
349 + DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(1)),
350 + DUMP_WED(WED_RTQM_IGRS2_I2HW_PKT_CNT),
351 + DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(0)),
352 + DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(1)),
353 + DUMP_WED(WED_RTQM_IGRS2_FDROP_CNT),
354 +
355 + DUMP_STR("WED Route QM IGRS3(DEBUG)"),
356 + DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
357 + DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(0)),
358 + DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(1)),
359 + DUMP_WED(WED_RTQM_IGRS3_I2HW_PKT_CNT),
360 + DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(0)),
361 + DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(1)),
362 + DUMP_WED(WED_RTQM_IGRS3_FDROP_CNT),
363 + };
364 + struct mtk_wed_hw *hw = s->private;
365 + struct mtk_wed_device *dev = hw->wed_dev;
366 +
367 + if (dev)
368 + dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
369 +
370 + return 0;
371 +}
372 +DEFINE_SHOW_ATTRIBUTE(wed_rtqm);
373 +
374 +static int
375 +wed_rro_show(struct seq_file *s, void *data)
376 +{
377 + static const struct reg_dump regs[] = {
378 + DUMP_STR("RRO/IND CMD CNT"),
379 + DUMP_WED(WED_RX_IND_CMD_CNT(1)),
380 + DUMP_WED(WED_RX_IND_CMD_CNT(2)),
381 + DUMP_WED(WED_RX_IND_CMD_CNT(3)),
382 + DUMP_WED(WED_RX_IND_CMD_CNT(4)),
383 + DUMP_WED(WED_RX_IND_CMD_CNT(5)),
384 + DUMP_WED(WED_RX_IND_CMD_CNT(6)),
385 + DUMP_WED(WED_RX_IND_CMD_CNT(7)),
386 + DUMP_WED(WED_RX_IND_CMD_CNT(8)),
387 + DUMP_WED_MASK(WED_RX_IND_CMD_CNT(9),
388 + WED_IND_CMD_MAGIC_CNT_FAIL_CNT),
389 +
390 + DUMP_WED(WED_RX_ADDR_ELEM_CNT(0)),
391 + DUMP_WED_MASK(WED_RX_ADDR_ELEM_CNT(1),
392 + WED_ADDR_ELEM_SIG_FAIL_CNT),
393 + DUMP_WED(WED_RX_MSDU_PG_CNT(1)),
394 + DUMP_WED(WED_RX_MSDU_PG_CNT(2)),
395 + DUMP_WED(WED_RX_MSDU_PG_CNT(3)),
396 + DUMP_WED(WED_RX_MSDU_PG_CNT(4)),
397 + DUMP_WED(WED_RX_MSDU_PG_CNT(5)),
398 + DUMP_WED_MASK(WED_RX_PN_CHK_CNT,
399 + WED_PN_CHK_FAIL_CNT),
400 + };
401 + struct mtk_wed_hw *hw = s->private;
402 + struct mtk_wed_device *dev = hw->wed_dev;
403 +
404 + if (dev)
405 + dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
406 +
407 + return 0;
408 +}
409 +DEFINE_SHOW_ATTRIBUTE(wed_rro);
410 +
411 +static int
412 mtk_wed_reg_set(void *data, u64 val)
413 {
414 struct mtk_wed_hw *hw = data;
415 @@ -266,7 +624,16 @@ void mtk_wed_hw_add_debugfs(struct mtk_w
416 debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
417 debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval);
418 debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops);
419 - if (!mtk_wed_is_v1(hw))
420 + if (!mtk_wed_is_v1(hw)) {
421 debugfs_create_file_unsafe("rxinfo", 0400, dir, hw,
422 &wed_rxinfo_fops);
423 + if (mtk_wed_is_v3_or_greater(hw)) {
424 + debugfs_create_file_unsafe("amsdu", 0400, dir, hw,
425 + &wed_amsdu_fops);
426 + debugfs_create_file_unsafe("rtqm", 0400, dir, hw,
427 + &wed_rtqm_fops);
428 + debugfs_create_file_unsafe("rro", 0400, dir, hw,
429 + &wed_rro_fops);
430 + }
431 + }
432 }
Staging tree of Chuanhong Guo