git.openwrt.org Git - openwrt/staging/svanheule.git/blob

   1 From 035a4db85bbf28ba1452c49c9f8d05a085f2544b Mon Sep 17 00:00:00 2001
   2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
   3 Date: Tue, 26 Apr 2016 17:40:05 +0530
   4 Subject: [PATCH 18/93] boards: ls1012aqds: Enable SDHC_CD in brdcfg10 of FPGA
   5
   6 Default configuration of brdcfg10 in FPGA does not enable SDHC_CD
   7 signal.
   8
   9 Enable SDHC_CD by default during boot sequence.
  10
  11 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
  12 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  13 ---
  14  board/freescale/ls1012aqds/ls1012aqds.c |   12 ++++++++++++
  15  include/configs/ls1012aqds.h            |    3 +++
  16  2 files changed, 15 insertions(+)
  17
  18 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
  19 index ffcd0d8..6d5fef8 100644
  20 --- a/board/freescale/ls1012aqds/ls1012aqds.c
  21 +++ b/board/freescale/ls1012aqds/ls1012aqds.c
  22 @@ -154,6 +154,18 @@ int board_early_init_f(void)
  23         return 0;
  24  }
  25
  26 +#ifdef CONFIG_MISC_INIT_R
  27 +int misc_init_r(void)
  28 +{
  29 +       u8 mux_sdhc_cd = 0x80;
  30 +
  31 +       i2c_set_bus_num(0);
  32 +
  33 +       i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
  34 +       return 0;
  35 +}
  36 +#endif
  37 +
  38  int board_init(void)
  39  {
  40         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
  41 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
  42 index fdada18..bb433de 100644
  43 --- a/include/configs/ls1012aqds.h
  44 +++ b/include/configs/ls1012aqds.h
  45 @@ -27,6 +27,7 @@
  46  #endif
  47
  48  #define CONFIG_QIXIS_I2C_ACCESS
  49 +#define CONFIG_SYS_I2C_FPGA_ADDR       0x66
  50
  51  /*
  52   * I2C bus multiplexer
  53 @@ -145,4 +146,6 @@
  54  #define CONFIG_SYS_MEMTEST_START       0x80000000
  55  #define CONFIG_SYS_MEMTEST_END         0x9fffffff
  56
  57 +#define CONFIG_MISC_INIT_R
  58 +
  59  #endif /* __LS1012AQDS_H__ */
  60 --
  61 1.7.9.5
  62