git.openwrt.org Git - openwrt/staging/dangole.git/blob

   1 From 4f3701fc599820568ba4395070d34e4248800fc0 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Wed, 2 Feb 2022 01:03:35 +0100
   4 Subject: [PATCH 16/16] net: dsa: qca8k: introduce qca8k_bulk_read/write
   5  function
   6
   7 Introduce qca8k_bulk_read/write() function to use mgmt Ethernet way to
   8 read/write packet in bulk. Make use of this new function in the fdb
   9 function and while at it reduce the reg for fdb_read from 4 to 3 as the
  10 max bit for the ARL(fdb) table is 83 bits.
  11
  12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  13 Signed-off-by: David S. Miller <davem@davemloft.net>
  14 ---
  15  drivers/net/dsa/qca8k.c | 55 ++++++++++++++++++++++++++++++++---------
  16  1 file changed, 43 insertions(+), 12 deletions(-)
  17
  18 --- a/drivers/net/dsa/qca8k.c
  19 +++ b/drivers/net/dsa/qca8k.c
  20 @@ -412,6 +412,43 @@ qca8k_regmap_update_bits_eth(struct qca8
  21  }
  22
  23  static int
  24 +qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
  25 +{
  26 +       int i, count = len / sizeof(u32), ret;
  27 +
  28 +       if (priv->mgmt_master && !qca8k_read_eth(priv, reg, val, len))
  29 +               return 0;
  30 +
  31 +       for (i = 0; i < count; i++) {
  32 +               ret = regmap_read(priv->regmap, reg + (i * 4), val + i);
  33 +               if (ret < 0)
  34 +                       return ret;
  35 +       }
  36 +
  37 +       return 0;
  38 +}
  39 +
  40 +static int
  41 +qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
  42 +{
  43 +       int i, count = len / sizeof(u32), ret;
  44 +       u32 tmp;
  45 +
  46 +       if (priv->mgmt_master && !qca8k_write_eth(priv, reg, val, len))
  47 +               return 0;
  48 +
  49 +       for (i = 0; i < count; i++) {
  50 +               tmp = val[i];
  51 +
  52 +               ret = regmap_write(priv->regmap, reg + (i * 4), tmp);
  53 +               if (ret < 0)
  54 +                       return ret;
  55 +       }
  56 +
  57 +       return 0;
  58 +}
  59 +
  60 +static int
  61  qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
  62  {
  63         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
  64 @@ -546,17 +583,13 @@ qca8k_busy_wait(struct qca8k_priv *priv,
  65  static int
  66  qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
  67  {
  68 -       u32 reg[4], val;
  69 -       int i, ret;
  70 +       u32 reg[3];
  71 +       int ret;
  72
  73         /* load the ARL table into an array */
  74 -       for (i = 0; i < 4; i++) {
  75 -               ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
  76 -               if (ret < 0)
  77 -                       return ret;
  78 -
  79 -               reg[i] = val;
  80 -       }
  81 +       ret = qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
  82 +       if (ret)
  83 +               return ret;
  84
  85         /* vid - 83:72 */
  86         fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
  87 @@ -580,7 +613,6 @@ qca8k_fdb_write(struct qca8k_priv *priv,
  88                 u8 aging)
  89  {
  90         u32 reg[3] = { 0 };
  91 -       int i;
  92
  93         /* vid - 83:72 */
  94         reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
  95 @@ -597,8 +629,7 @@ qca8k_fdb_write(struct qca8k_priv *priv,
  96         reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
  97
  98         /* load the array into the ARL table */
  99 -       for (i = 0; i < 3; i++)
 100 -               qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
 101 +       qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
 102  }
 103
 104  static int