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1 From 948a288897015fb3ee63b3f720b396b590c17fd7 Mon Sep 17 00:00:00 2001
2 From: Maso Huang <maso.huang@mediatek.com>
3 Date: Thu, 17 Aug 2023 18:13:34 +0800
4 Subject: [PATCH 2/9] ASoC: mediatek: mt7986: support etdm in platform driver
5
6 Add mt7986 etdm dai driver support.
7
8 Signed-off-by: Maso Huang <maso.huang@mediatek.com>
9 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
10 Link: https://lore.kernel.org/r/20230817101338.18782-3-maso.huang@mediatek.com
11 Signed-off-by: Mark Brown <broonie@kernel.org>
12 ---
13 sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 411 ++++++++++++++++++++
14 1 file changed, 411 insertions(+)
15 create mode 100644 sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
16
17 --- /dev/null
18 +++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
19 @@ -0,0 +1,411 @@
20 +// SPDX-License-Identifier: GPL-2.0
21 +/*
22 + * MediaTek ALSA SoC Audio DAI eTDM Control
23 + *
24 + * Copyright (c) 2023 MediaTek Inc.
25 + * Authors: Vic Wu <vic.wu@mediatek.com>
26 + * Maso Huang <maso.huang@mediatek.com>
27 + */
28 +
29 +#include <linux/bitfield.h>
30 +#include <linux/bitops.h>
31 +#include <linux/regmap.h>
32 +#include <sound/pcm_params.h>
33 +#include "mt7986-afe-common.h"
34 +#include "mt7986-reg.h"
35 +
36 +#define HOPPING_CLK 0
37 +#define APLL_CLK 1
38 +#define MTK_DAI_ETDM_FORMAT_I2S 0
39 +#define MTK_DAI_ETDM_FORMAT_DSPA 4
40 +#define MTK_DAI_ETDM_FORMAT_DSPB 5
41 +
42 +enum {
43 + MTK_ETDM_RATE_8K = 0,
44 + MTK_ETDM_RATE_12K = 1,
45 + MTK_ETDM_RATE_16K = 2,
46 + MTK_ETDM_RATE_24K = 3,
47 + MTK_ETDM_RATE_32K = 4,
48 + MTK_ETDM_RATE_48K = 5,
49 + MTK_ETDM_RATE_96K = 7,
50 + MTK_ETDM_RATE_192K = 9,
51 + MTK_ETDM_RATE_11K = 16,
52 + MTK_ETDM_RATE_22K = 17,
53 + MTK_ETDM_RATE_44K = 18,
54 + MTK_ETDM_RATE_88K = 19,
55 + MTK_ETDM_RATE_176K = 20,
56 +};
57 +
58 +struct mtk_dai_etdm_priv {
59 + bool bck_inv;
60 + bool lrck_inv;
61 + bool slave_mode;
62 + unsigned int format;
63 +};
64 +
65 +static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate)
66 +{
67 + switch (rate) {
68 + case 8000:
69 + return MTK_ETDM_RATE_8K;
70 + case 11025:
71 + return MTK_ETDM_RATE_11K;
72 + case 12000:
73 + return MTK_ETDM_RATE_12K;
74 + case 16000:
75 + return MTK_ETDM_RATE_16K;
76 + case 22050:
77 + return MTK_ETDM_RATE_22K;
78 + case 24000:
79 + return MTK_ETDM_RATE_24K;
80 + case 32000:
81 + return MTK_ETDM_RATE_32K;
82 + case 44100:
83 + return MTK_ETDM_RATE_44K;
84 + case 48000:
85 + return MTK_ETDM_RATE_48K;
86 + case 88200:
87 + return MTK_ETDM_RATE_88K;
88 + case 96000:
89 + return MTK_ETDM_RATE_96K;
90 + case 176400:
91 + return MTK_ETDM_RATE_176K;
92 + case 192000:
93 + return MTK_ETDM_RATE_192K;
94 + default:
95 + dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
96 + __func__, rate, MTK_ETDM_RATE_48K);
97 + return MTK_ETDM_RATE_48K;
98 + }
99 +}
100 +
101 +static int get_etdm_wlen(unsigned int bitwidth)
102 +{
103 + return bitwidth <= 16 ? 16 : 32;
104 +}
105 +
106 +/* dai component */
107 +/* interconnection */
108 +
109 +static const struct snd_kcontrol_new o124_mix[] = {
110 + SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0),
111 +};
112 +
113 +static const struct snd_kcontrol_new o125_mix[] = {
114 + SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0),
115 +};
116 +
117 +static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
118 +
119 + /* DL */
120 + SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0),
121 + SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0),
122 + /* UL */
123 + SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)),
124 + SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)),
125 +};
126 +
127 +static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
128 + {"I150", NULL, "ETDM Capture"},
129 + {"I151", NULL, "ETDM Capture"},
130 + {"ETDM Playback", NULL, "O124"},
131 + {"ETDM Playback", NULL, "O125"},
132 + {"O124", "I032_Switch", "I032"},
133 + {"O125", "I033_Switch", "I033"},
134 +};
135 +
136 +/* dai ops */
137 +static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
138 + struct snd_soc_dai *dai)
139 +{
140 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
141 + struct mt7986_afe_private *afe_priv = afe->platform_priv;
142 + int ret;
143 +
144 + ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
145 + if (ret)
146 + return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
147 +
148 + regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0);
149 + regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0);
150 +
151 + return 0;
152 +}
153 +
154 +static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
155 + struct snd_soc_dai *dai)
156 +{
157 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
158 + struct mt7986_afe_private *afe_priv = afe->platform_priv;
159 +
160 + regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK,
161 + CLK_OUT5_PDN);
162 + regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK,
163 + CLK_IN5_PDN);
164 +
165 + clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
166 +}
167 +
168 +static unsigned int get_etdm_ch_fixup(unsigned int channels)
169 +{
170 + if (channels > 16)
171 + return 24;
172 + else if (channels > 8)
173 + return 16;
174 + else if (channels > 4)
175 + return 8;
176 + else if (channels > 2)
177 + return 4;
178 + else
179 + return 2;
180 +}
181 +
182 +static int mtk_dai_etdm_config(struct mtk_base_afe *afe,
183 + struct snd_pcm_hw_params *params,
184 + struct snd_soc_dai *dai,
185 + int stream)
186 +{
187 + struct mt7986_afe_private *afe_priv = afe->platform_priv;
188 + struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
189 + unsigned int rate = params_rate(params);
190 + unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate);
191 + unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate);
192 + unsigned int channels = params_channels(params);
193 + unsigned int bit_width = params_width(params);
194 + unsigned int wlen = get_etdm_wlen(bit_width);
195 + unsigned int val = 0;
196 + unsigned int mask = 0;
197 +
198 + dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n",
199 + __func__, stream, rate, bit_width);
200 +
201 + /* CON0 */
202 + mask |= ETDM_BIT_LEN_MASK;
203 + val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1);
204 + mask |= ETDM_WRD_LEN_MASK;
205 + val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1);
206 + mask |= ETDM_FMT_MASK;
207 + val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format);
208 + mask |= ETDM_CH_NUM_MASK;
209 + val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1);
210 + mask |= RELATCH_SRC_MASK;
211 + val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK);
212 +
213 + switch (stream) {
214 + case SNDRV_PCM_STREAM_PLAYBACK:
215 + /* set ETDM_OUT5_CON0 */
216 + regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val);
217 +
218 + /* set ETDM_OUT5_CON4 */
219 + regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
220 + OUT_RELATCH_MASK, OUT_RELATCH(afe_rate));
221 + regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
222 + OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK));
223 + regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
224 + OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate));
225 +
226 + /* set ETDM_OUT5_CON5 */
227 + regmap_update_bits(afe->regmap, ETDM_OUT5_CON5,
228 + ETDM_CLK_DIV_MASK, ETDM_CLK_DIV);
229 + break;
230 + case SNDRV_PCM_STREAM_CAPTURE:
231 + /* set ETDM_IN5_CON0 */
232 + regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val);
233 + regmap_update_bits(afe->regmap, ETDM_IN5_CON0,
234 + ETDM_SYNC_MASK, ETDM_SYNC);
235 +
236 + /* set ETDM_IN5_CON2 */
237 + regmap_update_bits(afe->regmap, ETDM_IN5_CON2,
238 + IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK));
239 +
240 + /* set ETDM_IN5_CON3 */
241 + regmap_update_bits(afe->regmap, ETDM_IN5_CON3,
242 + IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate));
243 +
244 + /* set ETDM_IN5_CON4 */
245 + regmap_update_bits(afe->regmap, ETDM_IN5_CON4,
246 + IN_RELATCH_MASK, IN_RELATCH(afe_rate));
247 + break;
248 + default:
249 + break;
250 + }
251 +
252 + return 0;
253 +}
254 +
255 +static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
256 + struct snd_pcm_hw_params *params,
257 + struct snd_soc_dai *dai)
258 +{
259 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
260 +
261 + mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
262 + mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
263 +
264 + return 0;
265 +}
266 +
267 +static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
268 + struct snd_soc_dai *dai)
269 +{
270 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
271 +
272 + dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
273 + switch (cmd) {
274 + case SNDRV_PCM_TRIGGER_START:
275 + case SNDRV_PCM_TRIGGER_RESUME:
276 + regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
277 + ETDM_EN);
278 + regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
279 + ETDM_EN);
280 + break;
281 + case SNDRV_PCM_TRIGGER_STOP:
282 + case SNDRV_PCM_TRIGGER_SUSPEND:
283 + regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
284 + 0);
285 + regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
286 + 0);
287 + break;
288 + default:
289 + break;
290 + }
291 +
292 + return 0;
293 +}
294 +
295 +static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
296 +{
297 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
298 + struct mt7986_afe_private *afe_priv = afe->platform_priv;
299 + struct mtk_dai_etdm_priv *etdm_data;
300 + void *priv_data;
301 +
302 + switch (dai->id) {
303 + case MT7986_DAI_ETDM:
304 + break;
305 + default:
306 + dev_warn(afe->dev, "%s(), id %d not support\n",
307 + __func__, dai->id);
308 + return -EINVAL;
309 + }
310 +
311 + priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv),
312 + GFP_KERNEL);
313 + if (!priv_data)
314 + return -ENOMEM;
315 +
316 + afe_priv->dai_priv[dai->id] = priv_data;
317 + etdm_data = afe_priv->dai_priv[dai->id];
318 +
319 + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
320 + case SND_SOC_DAIFMT_I2S:
321 + etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
322 + break;
323 + case SND_SOC_DAIFMT_DSP_A:
324 + etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
325 + break;
326 + case SND_SOC_DAIFMT_DSP_B:
327 + etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
328 + break;
329 + default:
330 + return -EINVAL;
331 + }
332 +
333 + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
334 + case SND_SOC_DAIFMT_NB_NF:
335 + etdm_data->bck_inv = false;
336 + etdm_data->lrck_inv = false;
337 + break;
338 + case SND_SOC_DAIFMT_NB_IF:
339 + etdm_data->bck_inv = false;
340 + etdm_data->lrck_inv = true;
341 + break;
342 + case SND_SOC_DAIFMT_IB_NF:
343 + etdm_data->bck_inv = true;
344 + etdm_data->lrck_inv = false;
345 + break;
346 + case SND_SOC_DAIFMT_IB_IF:
347 + etdm_data->bck_inv = true;
348 + etdm_data->lrck_inv = true;
349 + break;
350 + default:
351 + return -EINVAL;
352 + }
353 +
354 + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
355 + case SND_SOC_DAIFMT_CBM_CFM:
356 + etdm_data->slave_mode = true;
357 + break;
358 + case SND_SOC_DAIFMT_CBS_CFS:
359 + etdm_data->slave_mode = false;
360 + break;
361 + default:
362 + return -EINVAL;
363 + }
364 +
365 + return 0;
366 +}
367 +
368 +static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
369 + .startup = mtk_dai_etdm_startup,
370 + .shutdown = mtk_dai_etdm_shutdown,
371 + .hw_params = mtk_dai_etdm_hw_params,
372 + .trigger = mtk_dai_etdm_trigger,
373 + .set_fmt = mtk_dai_etdm_set_fmt,
374 +};
375 +
376 +/* dai driver */
377 +#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
378 + SNDRV_PCM_RATE_88200 |\
379 + SNDRV_PCM_RATE_96000 |\
380 + SNDRV_PCM_RATE_176400 |\
381 + SNDRV_PCM_RATE_192000)
382 +
383 +#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
384 + SNDRV_PCM_FMTBIT_S24_LE |\
385 + SNDRV_PCM_FMTBIT_S32_LE)
386 +
387 +static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
388 + {
389 + .name = "ETDM",
390 + .id = MT7986_DAI_ETDM,
391 + .capture = {
392 + .stream_name = "ETDM Capture",
393 + .channels_min = 1,
394 + .channels_max = 2,
395 + .rates = MTK_ETDM_RATES,
396 + .formats = MTK_ETDM_FORMATS,
397 + },
398 + .playback = {
399 + .stream_name = "ETDM Playback",
400 + .channels_min = 1,
401 + .channels_max = 2,
402 + .rates = MTK_ETDM_RATES,
403 + .formats = MTK_ETDM_FORMATS,
404 + },
405 + .ops = &mtk_dai_etdm_ops,
406 + .symmetric_rate = 1,
407 + .symmetric_sample_bits = 1,
408 + },
409 +};
410 +
411 +int mt7986_dai_etdm_register(struct mtk_base_afe *afe)
412 +{
413 + struct mtk_base_afe_dai *dai;
414 +
415 + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
416 + if (!dai)
417 + return -ENOMEM;
418 +
419 + list_add(&dai->list, &afe->sub_dais);
420 +
421 + dai->dai_drivers = mtk_dai_etdm_driver;
422 + dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
423 +
424 + dai->dapm_widgets = mtk_dai_etdm_widgets;
425 + dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
426 + dai->dapm_routes = mtk_dai_etdm_routes;
427 + dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
428 +
429 + return 0;
430 +}
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