git.openwrt.org Git - openwrt/staging/blogic.git/blob

   1 From e663e06bd3f21e64bc2163910f626af68add6308 Mon Sep 17 00:00:00 2001
   2 From: Anand Gore <anand.gore@broadcom.com>
   3 Date: Wed, 1 Jun 2022 13:19:56 -0700
   4 Subject: [PATCH] ARM64: dts: Add DTS files for bcmbca SoC BCM6858
   5
   6 Add DTS for ARMv8 based broadband SoC BCM6858. bcm6858.dtsi is the SoC
   7 description DTS header and bcm96858.dts is a simple DTS file for
   8 Broadcom BCM96858 Reference board that only enables the UART port.
   9
  10 Signed-off-by: Anand Gore <anand.gore@broadcom.com>
  11 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  12 ---
  13  arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
  14  .../boot/dts/broadcom/bcmbca/bcm6858.dtsi     | 121 ++++++++++++++++++
  15  .../boot/dts/broadcom/bcmbca/bcm96858.dts     |  30 +++++
  16  3 files changed, 153 insertions(+), 1 deletion(-)
  17  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
  18  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
  19
  20 --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  21 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  22 @@ -1,3 +1,4 @@
  23  # SPDX-License-Identifier: GPL-2.0
  24  dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
  25 -                               bcm963158.dtb
  26 +                               bcm963158.dtb \
  27 +                               bcm96858.dtb
  28 --- /dev/null
  29 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
  30 @@ -0,0 +1,121 @@
  31 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  32 +/*
  33 + * Copyright 2022 Broadcom Ltd.
  34 + */
  35 +
  36 +#include <dt-bindings/interrupt-controller/irq.h>
  37 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  38 +
  39 +/ {
  40 +       compatible = "brcm,bcm6858", "brcm,bcmbca";
  41 +       #address-cells = <2>;
  42 +       #size-cells = <2>;
  43 +
  44 +       interrupt-parent = <&gic>;
  45 +
  46 +       cpus {
  47 +               #address-cells = <2>;
  48 +               #size-cells = <0>;
  49 +
  50 +               B53_0: cpu@0 {
  51 +                       compatible = "brcm,brahma-b53";
  52 +                       device_type = "cpu";
  53 +                       reg = <0x0 0x0>;
  54 +                       next-level-cache = <&L2_0>;
  55 +                       enable-method = "psci";
  56 +               };
  57 +
  58 +               B53_1: cpu@1 {
  59 +                       compatible = "brcm,brahma-b53";
  60 +                       device_type = "cpu";
  61 +                       reg = <0x0 0x1>;
  62 +                       next-level-cache = <&L2_0>;
  63 +                       enable-method = "psci";
  64 +               };
  65 +
  66 +               B53_2: cpu@2 {
  67 +                       compatible = "brcm,brahma-b53";
  68 +                       device_type = "cpu";
  69 +                       reg = <0x0 0x2>;
  70 +                       next-level-cache = <&L2_0>;
  71 +                       enable-method = "psci";
  72 +               };
  73 +
  74 +               B53_3: cpu@3 {
  75 +                       compatible = "brcm,brahma-b53";
  76 +                       device_type = "cpu";
  77 +                       reg = <0x0 0x3>;
  78 +                       next-level-cache = <&L2_0>;
  79 +                       enable-method = "psci";
  80 +               };
  81 +               L2_0: l2-cache0 {
  82 +                       compatible = "cache";
  83 +               };
  84 +       };
  85 +
  86 +       timer {
  87 +               compatible = "arm,armv8-timer";
  88 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  89 +                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90 +                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91 +                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  92 +       };
  93 +
  94 +       pmu: pmu {
  95 +               compatible = "arm,armv8-pmuv3";
  96 +               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  97 +                       <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  98 +                       <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  99 +                       <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 100 +               interrupt-affinity = <&B53_0>, <&B53_1>,
 101 +                       <&B53_2>, <&B53_3>;
 102 +       };
 103 +
 104 +       clocks: clocks {
 105 +               periph_clk:periph-clk {
 106 +                       compatible = "fixed-clock";
 107 +                       #clock-cells = <0>;
 108 +                       clock-frequency = <200000000>;
 109 +               };
 110 +       };
 111 +
 112 +       psci {
 113 +               compatible = "arm,psci-0.2";
 114 +               method = "smc";
 115 +       };
 116 +
 117 +       axi@81000000 {
 118 +               compatible = "simple-bus";
 119 +               #address-cells = <1>;
 120 +               #size-cells = <1>;
 121 +               ranges = <0x0 0x0 0x81000000 0x8000>;
 122 +
 123 +               gic: interrupt-controller@1000 {
 124 +                       compatible = "arm,gic-400";
 125 +                       #interrupt-cells = <3>;
 126 +                       interrupt-controller;
 127 +                       reg = <0x1000 0x1000>, /* GICD */
 128 +                               <0x2000 0x2000>, /* GICC */
 129 +                               <0x4000 0x2000>, /* GICH */
 130 +                               <0x6000 0x2000>; /* GICV */
 131 +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
 132 +                                       IRQ_TYPE_LEVEL_HIGH)>;
 133 +               };
 134 +       };
 135 +
 136 +       bus@ff800000 {
 137 +               compatible = "simple-bus";
 138 +               #address-cells = <1>;
 139 +               #size-cells = <1>;
 140 +               ranges = <0x0 0x0 0xff800000 0x62000>;
 141 +
 142 +               uart0: serial@640 {
 143 +                       compatible = "brcm,bcm6345-uart";
 144 +                       reg = <0x640 0x18>;
 145 +                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 146 +                       clocks = <&periph_clk>;
 147 +                       clock-names = "refclk";
 148 +                       status = "disabled";
 149 +               };
 150 +       };
 151 +};
 152 --- /dev/null
 153 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
 154 @@ -0,0 +1,30 @@
 155 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 156 +/*
 157 + * Copyright 2022 Broadcom Ltd.
 158 + */
 159 +
 160 +/dts-v1/;
 161 +
 162 +#include "bcm6858.dtsi"
 163 +
 164 +/ {
 165 +       model = "Broadcom BCM96858 Reference Board";
 166 +       compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
 167 +
 168 +       aliases {
 169 +               serial0 = &uart0;
 170 +       };
 171 +
 172 +       chosen {
 173 +               stdout-path = "serial0:115200n8";
 174 +       };
 175 +
 176 +       memory@0 {
 177 +               device_type = "memory";
 178 +               reg = <0x0 0x0 0x0 0x08000000>;
 179 +       };
 180 +};
 181 +
 182 +&uart0 {
 183 +       status = "okay";
 184 +};