git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From c57a0efc17627d0077408544ded02674aefdecae Mon Sep 17 00:00:00 2001
   2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
   3 Date: Mon, 6 Jan 2020 16:59:02 +0200
   4 Subject: [PATCH] Revert "arm64: dts: LS1028a-rdb: use Ethernet PHY interrupt"
   5
   6 This reverts commit 841edb98671cfc4d6f010393ac429c78082ec4bd.
   7
   8 There are 2 separate issues with interrupts on the LS1028A-RDB board:
   9
  10 1. The GPIO1_DAT25 interrupt line is shared, so there is a real risk of
  11    race conditions if used in edge-triggered mode, as we currently do.
  12    This can be illustrated in the following setup:
  13    - Take 2 LS1028A-RDB boards
  14    - Connect swp0 to swp0, swp1 to swp1, swp2 to swp2
  15    - Plug/unplug the power to board 2, 10 times in a row. This will make
  16      the PHYs lose link simultaneously.
  17    - Notice that at one point, the net devices on board 1 remain in a
  18      state where not all the links are down (visible in "ip link"):
  19
  20      5: swp0: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
  21          link/ether be:97:36:d3:3d:70 brd ff:ff:ff:ff:ff:ff
  22      6: swp1: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
  23          link/ether be:97:36:d3:3d:71 brd ff:ff:ff:ff:ff:ff
  24      7: swp2: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state DOWN mode DEFAULT group default qlen 1000
  25          link/ether be:97:36:d3:3d:72 brd ff:ff:ff:ff:ff:ff
  26
  27    This cannot be solved by making the interrupts level-triggered,
  28    because the gpio-mpc8xxx controller only supports generating
  29    edge-triggered interrupts. So the effective reality is that we
  30    cannot not use shared interrupts connected to the gpio1
  31    interrupt-parent.
  32
  33 2. The uBUS1 and uBUS2 slots that share this interrupt line with the
  34    Ethernet PHYs are not pulled up by default, they are left floating on
  35    current revisions of the LS1028A-RDB boards. So sufficient electrical
  36    noise on these lines will make the CPLD think there's an interrupt
  37    request, so it asserts the GPIO1_DAT25 signal and leaves it asserted.
  38    This means that the PHYs on those boards will never have link when
  39    used in interrupt mode, because their IRQ will be masked by the uBUS
  40    line that is erroneously kept asserted. In poll mode this issue does
  41    not occur.
  42
  43 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
  44 ---
  45  arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 10 ----------
  46  1 file changed, 10 deletions(-)
  47
  48 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
  49 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
  50 @@ -206,8 +206,6 @@
  51                 #size-cells = <0>;
  52                 sgmii_phy0: ethernet-phy@2 {
  53                         reg = <0x2>;
  54 -                       interrupt-parent = <&gpio1>;
  55 -                       interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  56                 };
  57         };
  58  };
  59 @@ -219,26 +217,18 @@
  60  &enetc_mdio_pf3 {
  61         qsgmii_phy1: ethernet-phy@4 {
  62                 reg = <0x10>;
  63 -               interrupt-parent = <&gpio1>;
  64 -               interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  65         };
  66
  67         qsgmii_phy2: ethernet-phy@5 {
  68                 reg = <0x11>;
  69 -               interrupt-parent = <&gpio1>;
  70 -               interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  71         };
  72
  73         qsgmii_phy3: ethernet-phy@6 {
  74                 reg = <0x12>;
  75 -               interrupt-parent = <&gpio1>;
  76 -               interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  77         };
  78
  79         qsgmii_phy4: ethernet-phy@7 {
  80                 reg = <0x13>;
  81 -               interrupt-parent = <&gpio1>;
  82 -               interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  83         };
  84  };
  85