git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 3b3e35b279bee5e51580c648399e20323467f58c Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Mon, 15 May 2023 17:19:21 +0200
   4 Subject: [PATCH] ARM: dts: BCM5301X: Relicense AXI interrupts code to the GPL
   5  2.0+ / MIT
   6 MIME-Version: 1.0
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   9
  10 Those entries were added by:
  11 1. Hauke in commits dec378827c4a ("ARM: BCM5301X: Add IRQs to Broadcom's
  12    bus-axi in DTS file") and 1f80de6863ca ("ARM: BCM5301X: add IRQ
  13    numbers for PCIe controller")
  14 2. Florian in the commit 2cd0c0202f13 ("ARM: dts: BCM5301X: Add SRAB
  15    interrupts")
  16
  17 Move them to the bcm-ns.dtsi which uses dual licensing. That syncs more
  18 Northstar code to be based on the same licensing schema.
  19
  20 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  21 Cc: Hauke Mehrtens <hauke@hauke-m.de>
  22 Cc: Florian Fainelli <f.fainelli@gmail.com>
  23 Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
  24 Link: https://lore.kernel.org/r/20230515151921.25021-2-zajec5@gmail.com
  25 Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
  26 ---
  27  arch/arm/boot/dts/bcm-ns.dtsi   | 73 ++++++++++++++++++++++++++++++++
  28  arch/arm/boot/dts/bcm5301x.dtsi | 75 ---------------------------------
  29  2 files changed, 73 insertions(+), 75 deletions(-)
  30
  31 --- a/arch/arm/boot/dts/bcm-ns.dtsi
  32 +++ b/arch/arm/boot/dts/bcm-ns.dtsi
  33 @@ -92,6 +92,79 @@
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36
  37 +               #interrupt-cells = <1>;
  38 +               interrupt-map-mask = <0x000fffff 0xffff>;
  39 +               interrupt-map =
  40 +                       /* ChipCommon */
  41 +                       <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  42 +
  43 +                       /* Switch Register Access Block */
  44 +                       <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  45 +                       <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
  46 +                       <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
  47 +                       <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
  48 +                       <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
  49 +                       <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  50 +                       <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  51 +                       <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  52 +                       <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
  53 +                       <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
  54 +                       <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
  55 +                       <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
  56 +                       <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
  57 +
  58 +                       /* PCIe Controller 0 */
  59 +                       <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  60 +                       <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
  61 +                       <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
  62 +                       <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
  63 +                       <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
  64 +                       <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  65 +
  66 +                       /* PCIe Controller 1 */
  67 +                       <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
  68 +                       <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
  69 +                       <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
  70 +                       <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
  71 +                       <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  72 +                       <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  73 +
  74 +                       /* PCIe Controller 2 */
  75 +                       <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  76 +                       <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  77 +                       <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
  78 +                       <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  79 +                       <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  80 +                       <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
  81 +
  82 +                       /* USB 2.0 Controller */
  83 +                       <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
  84 +
  85 +                       /* USB 3.0 Controller */
  86 +                       <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
  87 +
  88 +                       /* Ethernet Controller 0 */
  89 +                       <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
  90 +
  91 +                       /* Ethernet Controller 1 */
  92 +                       <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
  93 +
  94 +                       /* Ethernet Controller 2 */
  95 +                       <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
  96 +
  97 +                       /* Ethernet Controller 3 */
  98 +                       <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
  99 +
 100 +                       /* NAND Controller */
 101 +                       <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 102 +                       <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 103 +                       <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 104 +                       <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 105 +                       <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 106 +                       <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 107 +                       <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 108 +                       <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 109 +
 110                 chipcommon: chipcommon@0 {
 111                         reg = <0x00000000 0x1000>;
 112
 113 --- a/arch/arm/boot/dts/bcm5301x.dtsi
 114 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
 115 @@ -3,8 +3,6 @@
 116   * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
 117   * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
 118   *
 119 - * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
 120 - *
 121   * Licensed under the GNU/GPL. See COPYING for details.
 122   */
 123
 124 @@ -72,79 +70,6 @@
 125         };
 126
 127         axi@18000000 {
 128 -               #interrupt-cells = <1>;
 129 -               interrupt-map-mask = <0x000fffff 0xffff>;
 130 -               interrupt-map =
 131 -                       /* ChipCommon */
 132 -                       <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 133 -
 134 -                       /* Switch Register Access Block */
 135 -                       <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 136 -                       <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 137 -                       <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 138 -                       <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 139 -                       <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 140 -                       <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 141 -                       <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 142 -                       <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 143 -                       <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 144 -                       <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 145 -                       <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 146 -                       <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 147 -                       <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 148 -
 149 -                       /* PCIe Controller 0 */
 150 -                       <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 151 -                       <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 152 -                       <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 153 -                       <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 154 -                       <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 155 -                       <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 156 -
 157 -                       /* PCIe Controller 1 */
 158 -                       <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 159 -                       <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 160 -                       <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 161 -                       <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 162 -                       <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 163 -                       <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 164 -
 165 -                       /* PCIe Controller 2 */
 166 -                       <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 167 -                       <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 168 -                       <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 169 -                       <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 170 -                       <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 171 -                       <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 172 -
 173 -                       /* USB 2.0 Controller */
 174 -                       <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 175 -
 176 -                       /* USB 3.0 Controller */
 177 -                       <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 178 -
 179 -                       /* Ethernet Controller 0 */
 180 -                       <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 181 -
 182 -                       /* Ethernet Controller 1 */
 183 -                       <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 184 -
 185 -                       /* Ethernet Controller 2 */
 186 -                       <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 187 -
 188 -                       /* Ethernet Controller 3 */
 189 -                       <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 190 -
 191 -                       /* NAND Controller */
 192 -                       <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 193 -                       <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 194 -                       <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 195 -                       <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 196 -                       <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 197 -                       <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 198 -                       <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 199 -                       <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 200 -
 201                 pcie2: pcie@14000 {
 202                         reg = <0x00014000 0x1000>;
 203                 };