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1 From 3cf9e2daca330a0ba89d3793ceb09037c788db46 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 20 May 2022 11:22:49 +0800
4 Subject: [PATCH 10/25] pinctrl: mtmips: add support for MediaTek MT7621 SoC
5
6 This patch adds pinctrl support for MediaTek MT7621 SoC.
7 The MT7621 SoC supports pinconf, but it is not the same as mt7628.
8
9 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
11 ---
12 drivers/pinctrl/mtmips/Kconfig | 9 +
13 drivers/pinctrl/mtmips/Makefile | 1 +
14 drivers/pinctrl/mtmips/pinctrl-mt7621.c | 306 ++++++++++++++++++
15 .../pinctrl/mtmips/pinctrl-mtmips-common.c | 4 +-
16 .../pinctrl/mtmips/pinctrl-mtmips-common.h | 12 +
17 5 files changed, 330 insertions(+), 2 deletions(-)
18 create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7621.c
19
20 --- a/drivers/pinctrl/mtmips/Kconfig
21 +++ b/drivers/pinctrl/mtmips/Kconfig
22 @@ -12,6 +12,15 @@ config PINCTRL_MT7620
23 The driver is controlled by a device tree node which contains
24 the pin mux functions for each available pin groups.
25
26 +config PINCTRL_MT7621
27 + bool "MediaTek MT7621 pin control driver"
28 + select PINCTRL_MTMIPS
29 + depends on SOC_MT7621 && PINCTRL_GENERIC
30 + help
31 + Support pin multiplexing control on MediaTek MT7621.
32 + The driver is controlled by a device tree node which contains
33 + the pin mux functions for each available pin groups.
34 +
35 config PINCTRL_MT7628
36 bool "MediaTek MT7628 pin control driver"
37 select PINCTRL_MTMIPS
38 --- a/drivers/pinctrl/mtmips/Makefile
39 +++ b/drivers/pinctrl/mtmips/Makefile
40 @@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_MTMIPS) += pinctrl-
41
42 # SoC Drivers
43 obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
44 +obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o
45 obj-$(CONFIG_PINCTRL_MT7628) += pinctrl-mt7628.o
46 --- /dev/null
47 +++ b/drivers/pinctrl/mtmips/pinctrl-mt7621.c
48 @@ -0,0 +1,306 @@
49 +// SPDX-License-Identifier: GPL-2.0
50 +/*
51 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
52 + *
53 + * Author: Weijie Gao <weijie.gao@mediatek.com>
54 + */
55 +
56 +#include <dm.h>
57 +#include <dm/pinctrl.h>
58 +#include <dm/device_compat.h>
59 +#include <linux/bitops.h>
60 +#include <linux/io.h>
61 +
62 +#include "pinctrl-mtmips-common.h"
63 +
64 +#define SYSC_MAP_SIZE 0x100
65 +
66 +#define PAD_UART1_GPIO0_OFS 0x00
67 +#define PAD_UART3_I2C_OFS 0x04
68 +#define PAD_UART2_JTAG_OFS 0x08
69 +#define PAD_PERST_WDT_OFS 0x0c
70 +#define PAD_RGMII2_MDIO_OFS 0x10
71 +#define PAD_SDXC_SPI_OFS 0x14
72 +#define GPIOMODE_OFS 0x18
73 +#define PAD_BOPT_ESWINT_OFS 0x28
74 +
75 +#define ESWINT_SHIFT 20
76 +#define SDXC_SHIFT 18
77 +#define SPI_SHIFT 16
78 +#define RGMII2_SHIFT 15
79 +#define RGMII1_SHIFT 14
80 +#define MDIO_SHIFT 12
81 +#define PERST_SHIFT 10
82 +#define WDT_SHIFT 8
83 +#define JTAG_SHIFT 7
84 +#define UART2_SHIFT 5
85 +#define UART3_SHIFT 3
86 +#define I2C_SHIFT 2
87 +#define UART1_SHIFT 1
88 +#define GPIO0_SHIFT 0 /* Dummy */
89 +
90 +#define GM4_MASK 3
91 +
92 +#define E4_E2_M 0x03
93 +#define E4_E2_S 4
94 +#define PULL_UP BIT(3)
95 +#define PULL_DOWN BIT(2)
96 +#define SMT BIT(1)
97 +#define SR BIT(0)
98 +
99 +struct mt7621_pinctrl_priv {
100 + struct mtmips_pinctrl_priv mp;
101 +};
102 +
103 +#if CONFIG_IS_ENABLED(PINMUX)
104 +static const struct mtmips_pmx_func esw_int_grp[] = {
105 + FUNC("gpio", 1),
106 + FUNC("esw int", 0),
107 +};
108 +
109 +static const struct mtmips_pmx_func sdxc_grp[] = {
110 + FUNC("nand", 2),
111 + FUNC("gpio", 1),
112 + FUNC("sdxc", 0),
113 +};
114 +
115 +static const struct mtmips_pmx_func spi_grp[] = {
116 + FUNC("nand", 2),
117 + FUNC("gpio", 1),
118 + FUNC("spi", 0),
119 +};
120 +
121 +static const struct mtmips_pmx_func rgmii2_grp[] = {
122 + FUNC("gpio", 1),
123 + FUNC("rgmii", 0),
124 +};
125 +
126 +static const struct mtmips_pmx_func rgmii1_grp[] = {
127 + FUNC("gpio", 1),
128 + FUNC("rgmii", 0),
129 +};
130 +
131 +static const struct mtmips_pmx_func mdio_grp[] = {
132 + FUNC("gpio", 1),
133 + FUNC("mdio", 0),
134 +};
135 +
136 +static const struct mtmips_pmx_func perst_grp[] = {
137 + FUNC("refclk", 2),
138 + FUNC("gpio", 1),
139 + FUNC("pcie reset", 0),
140 +};
141 +
142 +static const struct mtmips_pmx_func wdt_grp[] = {
143 + FUNC("refclk", 2),
144 + FUNC("gpio", 1),
145 + FUNC("wdt rst", 0),
146 +};
147 +
148 +static const struct mtmips_pmx_func jtag_grp[] = {
149 + FUNC("gpio", 1),
150 + FUNC("jtag", 0),
151 +};
152 +
153 +static const struct mtmips_pmx_func uart2_grp[] = {
154 + FUNC("spdif", 3),
155 + FUNC("pcm", 2),
156 + FUNC("gpio", 1),
157 + FUNC("uart", 0),
158 +};
159 +
160 +static const struct mtmips_pmx_func uart3_grp[] = {
161 + FUNC("spdif", 3),
162 + FUNC("i2s", 2),
163 + FUNC("gpio", 1),
164 + FUNC("uart", 0),
165 +};
166 +
167 +static const struct mtmips_pmx_func i2c_grp[] = {
168 + FUNC("gpio", 1),
169 + FUNC("i2c", 0),
170 +};
171 +
172 +static const struct mtmips_pmx_func uart1_grp[] = {
173 + FUNC("gpio", 1),
174 + FUNC("uart", 0),
175 +};
176 +
177 +static const struct mtmips_pmx_func gpio0_grp[] = {
178 + FUNC("gpio", 0),
179 +};
180 +
181 +static const struct mtmips_pmx_group mt7621_pmx_data[] = {
182 + GRP_PCONF("esw int", esw_int_grp, GPIOMODE_OFS, ESWINT_SHIFT, 1,
183 + PAD_BOPT_ESWINT_OFS, 0),
184 + GRP_PCONF("sdxc", sdxc_grp, GPIOMODE_OFS, SDXC_SHIFT, GM4_MASK,
185 + PAD_SDXC_SPI_OFS, 16),
186 + GRP_PCONF("spi", spi_grp, GPIOMODE_OFS, SPI_SHIFT, GM4_MASK,
187 + PAD_SDXC_SPI_OFS, 0),
188 + GRP_PCONF("rgmii2", rgmii2_grp, GPIOMODE_OFS, RGMII2_SHIFT, 1,
189 + PAD_RGMII2_MDIO_OFS, 16),
190 + GRP("rgmii1", rgmii1_grp, GPIOMODE_OFS, RGMII1_SHIFT, 1),
191 + GRP_PCONF("mdio", mdio_grp, GPIOMODE_OFS, MDIO_SHIFT, GM4_MASK,
192 + PAD_RGMII2_MDIO_OFS, 0),
193 + GRP_PCONF("pcie reset", perst_grp, GPIOMODE_OFS, PERST_SHIFT, GM4_MASK,
194 + PAD_PERST_WDT_OFS, 16),
195 + GRP_PCONF("wdt", wdt_grp, GPIOMODE_OFS, WDT_SHIFT, GM4_MASK,
196 + PAD_PERST_WDT_OFS, 0),
197 + GRP_PCONF("jtag", jtag_grp, GPIOMODE_OFS, JTAG_SHIFT, 1,
198 + PAD_UART2_JTAG_OFS, 16),
199 + GRP_PCONF("uart2", uart2_grp, GPIOMODE_OFS, UART2_SHIFT, GM4_MASK,
200 + PAD_UART2_JTAG_OFS, 0),
201 + GRP_PCONF("uart3", uart3_grp, GPIOMODE_OFS, UART3_SHIFT, GM4_MASK,
202 + PAD_UART3_I2C_OFS, 16),
203 + GRP_PCONF("i2c", i2c_grp, GPIOMODE_OFS, I2C_SHIFT, 1,
204 + PAD_UART3_I2C_OFS, 0),
205 + GRP_PCONF("uart1", uart1_grp, GPIOMODE_OFS, UART1_SHIFT, 1,
206 + PAD_UART1_GPIO0_OFS, 16),
207 + GRP_PCONF("gpio0", gpio0_grp, GPIOMODE_OFS, GPIO0_SHIFT, 1,
208 + PAD_UART1_GPIO0_OFS, 0),
209 +};
210 +
211 +static int mt7621_get_groups_count(struct udevice *dev)
212 +{
213 + return ARRAY_SIZE(mt7621_pmx_data);
214 +}
215 +
216 +static const char *mt7621_get_group_name(struct udevice *dev,
217 + unsigned int selector)
218 +{
219 + return mt7621_pmx_data[selector].name;
220 +}
221 +#endif /* CONFIG_IS_ENABLED(PINMUX) */
222 +
223 +#if CONFIG_IS_ENABLED(PINCONF)
224 +static const struct pinconf_param mt7621_conf_params[] = {
225 + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
226 + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
227 + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
228 + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
229 + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
230 + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
231 + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
232 +};
233 +
234 +static const u32 mt7621_pconf_drv_strength_tbl[] = {2, 4, 6, 8};
235 +
236 +static int mt7621_pinconf_group_set(struct udevice *dev,
237 + unsigned int group_selector,
238 + unsigned int param, unsigned int arg)
239 +{
240 + struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
241 + const struct mtmips_pmx_group *grp = &mt7621_pmx_data[group_selector];
242 + u32 clr = 0, set = 0;
243 + int i;
244 +
245 + if (!grp->pconf_avail)
246 + return 0;
247 +
248 + switch (param) {
249 + case PIN_CONFIG_BIAS_DISABLE:
250 + clr = PULL_UP | PULL_DOWN;
251 + break;
252 +
253 + case PIN_CONFIG_BIAS_PULL_UP:
254 + clr = PULL_DOWN;
255 + set = PULL_UP;
256 + break;
257 +
258 + case PIN_CONFIG_BIAS_PULL_DOWN:
259 + clr = PULL_UP;
260 + set = PULL_DOWN;
261 + break;
262 +
263 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
264 + if (arg)
265 + set = SMT;
266 + else
267 + clr = SMT;
268 + break;
269 +
270 + case PIN_CONFIG_DRIVE_STRENGTH:
271 + for (i = 0; i < ARRAY_SIZE(mt7621_pconf_drv_strength_tbl); i++)
272 + if (mt7621_pconf_drv_strength_tbl[i] == arg)
273 + break;
274 +
275 + if (i >= ARRAY_SIZE(mt7621_pconf_drv_strength_tbl))
276 + return -EINVAL;
277 +
278 + clr = E4_E2_M << E4_E2_S;
279 + set = i << E4_E2_S;
280 + break;
281 +
282 + case PIN_CONFIG_SLEW_RATE:
283 + if (arg)
284 + set = SR;
285 + else
286 + clr = SR;
287 + break;
288 +
289 + default:
290 + return -EINVAL;
291 + }
292 +
293 + mtmips_pinctrl_reg_set(&priv->mp, grp->pconf_reg, grp->pconf_shift,
294 + clr, set);
295 +
296 + return 0;
297 +}
298 +#endif
299 +
300 +static int mt7621_pinctrl_probe(struct udevice *dev)
301 +{
302 + struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
303 + int ret = 0;
304 +
305 +#if CONFIG_IS_ENABLED(PINMUX)
306 + ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7621_pmx_data),
307 + mt7621_pmx_data);
308 +#endif /* CONFIG_IS_ENABLED(PINMUX) */
309 +
310 + return ret;
311 +}
312 +
313 +static int mt7621_pinctrl_of_to_plat(struct udevice *dev)
314 +{
315 + struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
316 +
317 + priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0);
318 +
319 + if (!priv->mp.base)
320 + return -EINVAL;
321 +
322 + return 0;
323 +}
324 +
325 +static const struct pinctrl_ops mt7621_pinctrl_ops = {
326 +#if CONFIG_IS_ENABLED(PINMUX)
327 + .get_groups_count = mt7621_get_groups_count,
328 + .get_group_name = mt7621_get_group_name,
329 + .get_functions_count = mtmips_get_functions_count,
330 + .get_function_name = mtmips_get_function_name,
331 + .pinmux_group_set = mtmips_pinmux_group_set,
332 +#endif /* CONFIG_IS_ENABLED(PINMUX) */
333 +#if CONFIG_IS_ENABLED(PINCONF)
334 + .pinconf_num_params = ARRAY_SIZE(mt7621_conf_params),
335 + .pinconf_params = mt7621_conf_params,
336 + .pinconf_group_set = mt7621_pinconf_group_set,
337 +#endif /* CONFIG_IS_ENABLED(PINCONF) */
338 + .set_state = pinctrl_generic_set_state,
339 +};
340 +
341 +static const struct udevice_id mt7621_pinctrl_ids[] = {
342 + { .compatible = "mediatek,mt7621-pinctrl" },
343 + { }
344 +};
345 +
346 +U_BOOT_DRIVER(mt7621_pinctrl) = {
347 + .name = "mt7621-pinctrl",
348 + .id = UCLASS_PINCTRL,
349 + .of_match = mt7621_pinctrl_ids,
350 + .of_to_plat = mt7621_pinctrl_of_to_plat,
351 + .ops = &mt7621_pinctrl_ops,
352 + .probe = mt7621_pinctrl_probe,
353 + .priv_auto = sizeof(struct mt7621_pinctrl_priv),
354 +};
355 --- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c
356 +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c
357 @@ -13,8 +13,8 @@
358
359 #include "pinctrl-mtmips-common.h"
360
361 -static void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
362 - u32 reg, u32 shift, u32 mask, u32 value)
363 +void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
364 + u32 reg, u32 shift, u32 mask, u32 value)
365 {
366 u32 val;
367
368 --- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h
369 +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h
370 @@ -22,6 +22,10 @@ struct mtmips_pmx_group {
371 u32 shift;
372 char mask;
373
374 + int pconf_avail;
375 + u32 pconf_reg;
376 + u32 pconf_shift;
377 +
378 int nfuncs;
379 const struct mtmips_pmx_func *funcs;
380 };
381 @@ -42,6 +46,14 @@ struct mtmips_pinctrl_priv {
382 { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
383 .funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs) }
384
385 +#define GRP_PCONF(_name, _funcs, _reg, _shift, _mask, _pconf_reg, _pconf_shift) \
386 + { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
387 + .funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs), .pconf_avail = 1, \
388 + .pconf_reg = (_pconf_reg), .pconf_shift = (_pconf_shift) }
389 +
390 +void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
391 + u32 reg, u32 shift, u32 mask, u32 value);
392 +
393 int mtmips_get_functions_count(struct udevice *dev);
394 const char *mtmips_get_function_name(struct udevice *dev,
395 unsigned int selector);
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