git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From b16dcc5f735739444da66149b473bb88fb44d4d9 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
   3 Date: Fri, 3 Jun 2022 16:49:09 +0100
   4 Subject: [PATCH] drm: vc4: 0 is a valid value for pixel_order_hvs5, so
   5  fix conditionals
   6
   7 vc4_plane_mode_set for HVS5 was using pixel_order unless pixel_order_hvs5
   8 was non-zero, except 0 is a valid value for the pixel_order.
   9
  10 Specify pixel_order_hvs5 for all formats and remove the conditional.
  11
  12 Reported-by: vrazzer <teamvraz@pipmail.net>
  13 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  14 ---
  15  drivers/gpu/drm/vc4/vc4_plane.c | 20 ++++++++++++++------
  16  1 file changed, 14 insertions(+), 6 deletions(-)
  17
  18 --- a/drivers/gpu/drm/vc4/vc4_plane.c
  19 +++ b/drivers/gpu/drm/vc4/vc4_plane.c
  20 @@ -65,11 +65,13 @@ static const struct hvs_format {
  21                 .drm = DRM_FORMAT_RGB565,
  22                 .hvs = HVS_PIXEL_FORMAT_RGB565,
  23                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  24 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XRGB,
  25         },
  26         {
  27                 .drm = DRM_FORMAT_BGR565,
  28                 .hvs = HVS_PIXEL_FORMAT_RGB565,
  29                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  30 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XBGR,
  31         },
  32         {
  33                 .drm = DRM_FORMAT_ARGB1555,
  34 @@ -87,56 +89,67 @@ static const struct hvs_format {
  35                 .drm = DRM_FORMAT_RGB888,
  36                 .hvs = HVS_PIXEL_FORMAT_RGB888,
  37                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  38 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XRGB,
  39         },
  40         {
  41                 .drm = DRM_FORMAT_BGR888,
  42                 .hvs = HVS_PIXEL_FORMAT_RGB888,
  43                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  44 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XBGR,
  45         },
  46         {
  47                 .drm = DRM_FORMAT_YUV422,
  48                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  49                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  50 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
  51         },
  52         {
  53                 .drm = DRM_FORMAT_YVU422,
  54                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  55                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  56 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
  57         },
  58         {
  59                 .drm = DRM_FORMAT_YUV420,
  60                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  61                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  62 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
  63         },
  64         {
  65                 .drm = DRM_FORMAT_YVU420,
  66                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  67                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  68 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
  69         },
  70         {
  71                 .drm = DRM_FORMAT_NV12,
  72                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
  73                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  74 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
  75         },
  76         {
  77                 .drm = DRM_FORMAT_NV21,
  78                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
  79                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  80 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
  81         },
  82         {
  83                 .drm = DRM_FORMAT_NV16,
  84                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
  85                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  86 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
  87         },
  88         {
  89                 .drm = DRM_FORMAT_NV61,
  90                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
  91                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  92 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
  93         },
  94         {
  95                 .drm = DRM_FORMAT_P030,
  96                 .hvs = HVS_PIXEL_FORMAT_YCBCR_10BIT,
  97                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  98 +               .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
  99                 .hvs5_only = true,
 100         },
 101         {
 102 @@ -1087,15 +1100,10 @@ static int vc4_plane_mode_set(struct drm
 103                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 104
 105         } else {
 106 -               u32 hvs_pixel_order = format->pixel_order;
 107 -
 108 -               if (format->pixel_order_hvs5)
 109 -                       hvs_pixel_order = format->pixel_order_hvs5;
 110 -
 111                 /* Control word */
 112                 vc4_dlist_write(vc4_state,
 113                                 SCALER_CTL0_VALID |
 114 -                               (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 115 +                               (format->pixel_order_hvs5 << SCALER_CTL0_ORDER_SHIFT) |
 116                                 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 117                                 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
 118                                 (vc4_state->is_unity ?