ea841d4248fe10c14716a714cb4b79eb176bacac
[openwrt/staging/ansuel.git] /
1 From 5a1ac160eab698846d90132422c6081d2802d2fd Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
3 Date: Fri, 28 Jul 2023 17:40:27 +0100
4 Subject: [PATCH 0636/1085] drm/panel: simple: Alter the timing for the Pi 7"
5 DSI display
6
7 vc4 has always fixed up the timing, so the values defined have
8 never actually appeared on the wire.
9 The display appears to want a slightly longer HFP, so extend
10 the timings and recompute the clock to give the same frame rate.
11
12 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
13 ---
14 drivers/gpu/drm/panel/panel-simple.c | 8 ++++----
15 1 file changed, 4 insertions(+), 4 deletions(-)
16
17 --- a/drivers/gpu/drm/panel/panel-simple.c
18 +++ b/drivers/gpu/drm/panel/panel-simple.c
19 @@ -3437,11 +3437,11 @@ static const struct panel_desc rocktech_
20 };
21
22 static const struct drm_display_mode raspberrypi_7inch_mode = {
23 - .clock = 25979400 / 1000,
24 + .clock = 27777,
25 .hdisplay = 800,
26 - .hsync_start = 800 + 2,
27 - .hsync_end = 800 + 2 + 2,
28 - .htotal = 800 + 2 + 2 + 46,
29 + .hsync_start = 800 + 59,
30 + .hsync_end = 800 + 59 + 2,
31 + .htotal = 800 + 59 + 2 + 46,
32 .vdisplay = 480,
33 .vsync_start = 480 + 7,
34 .vsync_end = 480 + 7 + 2,