git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From c0a440031d4314d1023c1b87f43a4233634eebdb Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Sun, 19 Mar 2023 12:57:15 +0000
   4 Subject: [PATCH] net: ethernet: mtk_eth_soc: set MDIO bus clock frequency
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Set MDIO bus clock frequency and allow setting a custom maximum
  10 frequency from device tree.
  11
  12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  13 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  14 Tested-by: Bjørn Mork <bjorn@mork.no>
  15 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  16 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  17 ---
  18  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 21 +++++++++++++++++++++
  19  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  7 +++++++
  20  2 files changed, 28 insertions(+)
  21
  22 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  23 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  24 @@ -745,8 +745,10 @@ static const struct phylink_mac_ops mtk_
  25
  26  static int mtk_mdio_init(struct mtk_eth *eth)
  27  {
  28 +       unsigned int max_clk = 2500000, divider;
  29         struct device_node *mii_np;
  30         int ret;
  31 +       u32 val;
  32
  33         mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
  34         if (!mii_np) {
  35 @@ -773,6 +775,25 @@ static int mtk_mdio_init(struct mtk_eth
  36         eth->mii_bus->parent = eth->dev;
  37
  38         snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
  39 +
  40 +       if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
  41 +               if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
  42 +                       dev_err(eth->dev, "MDIO clock frequency out of range");
  43 +                       ret = -EINVAL;
  44 +                       goto err_put_node;
  45 +               }
  46 +               max_clk = val;
  47 +       }
  48 +       divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
  49 +
  50 +       /* Configure MDC Divider */
  51 +       val = mtk_r32(eth, MTK_PPSC);
  52 +       val &= ~PPSC_MDC_CFG;
  53 +       val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
  54 +       mtk_w32(eth, val, MTK_PPSC);
  55 +
  56 +       dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
  57 +
  58         ret = of_mdiobus_register(eth->mii_bus, mii_np);
  59
  60  err_put_node:
  61 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  62 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  63 @@ -363,6 +363,13 @@
  64  #define RX_DMA_VTAG_V2         BIT(0)
  65  #define RX_DMA_L4_VALID_V2     BIT(2)
  66
  67 +/* PHY Polling and SMI Master Control registers */
  68 +#define MTK_PPSC               0x10000
  69 +#define PPSC_MDC_CFG           GENMASK(29, 24)
  70 +#define PPSC_MDC_TURBO         BIT(20)
  71 +#define MDC_MAX_FREQ           25000000
  72 +#define MDC_MAX_DIVIDER                63
  73 +
  74  /* PHY Indirect Access Control registers */
  75  #define MTK_PHY_IAC            0x10004
  76  #define PHY_IAC_ACCESS         BIT(31)