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1 From 9ee918eb911853c7b46cd84779d857988366e845 Mon Sep 17 00:00:00 2001
2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
3 Date: Mon, 6 Jan 2020 14:30:24 +0200
4 Subject: [PATCH] Revert "net: dsa: felix: Add PCS operations for PHYLINK"
5
6 This reverts commit 1082a3ef9e832cc52c4b0053c7c52453376f4830.
7
8 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
9 ---
10 drivers/net/dsa/ocelot/felix.c | 23 +--
11 drivers/net/dsa/ocelot/felix.h | 7 +-
12 drivers/net/dsa/ocelot/felix_vsc9959.c | 292 +--------------------------------
13 3 files changed, 8 insertions(+), 314 deletions(-)
14
15 --- a/drivers/net/dsa/ocelot/felix.c
16 +++ b/drivers/net/dsa/ocelot/felix.c
17 @@ -265,7 +265,7 @@ static int felix_get_ts_info(struct dsa_
18 static int felix_init_structs(struct felix *felix, int num_phys_ports)
19 {
20 struct ocelot *ocelot = &felix->ocelot;
21 - resource_size_t switch_base;
22 + resource_size_t base;
23 int port, i, err;
24
25 ocelot->num_phys_ports = num_phys_ports;
26 @@ -281,8 +281,7 @@ static int felix_init_structs(struct fel
27 ocelot->ops = felix->info->ops;
28 ocelot->quirks = felix->info->quirks;
29
30 - switch_base = pci_resource_start(felix->pdev,
31 - felix->info->switch_pci_bar);
32 + base = pci_resource_start(felix->pdev, felix->info->pci_bar);
33
34 for (i = 0; i < TARGET_MAX; i++) {
35 struct regmap *target;
36 @@ -293,8 +292,8 @@ static int felix_init_structs(struct fel
37
38 res = &felix->info->target_io_res[i];
39 res->flags = IORESOURCE_MEM;
40 - res->start += switch_base;
41 - res->end += switch_base;
42 + res->start += base;
43 + res->end += base;
44
45 target = ocelot_regmap_init(ocelot, res);
46 if (IS_ERR(target)) {
47 @@ -328,8 +327,8 @@ static int felix_init_structs(struct fel
48
49 res = &felix->info->port_io_res[port];
50 res->flags = IORESOURCE_MEM;
51 - res->start += switch_base;
52 - res->end += switch_base;
53 + res->start += base;
54 + res->end += base;
55
56 port_regs = devm_ioremap_resource(ocelot->dev, res);
57 if (IS_ERR(port_regs)) {
58 @@ -343,12 +342,6 @@ static int felix_init_structs(struct fel
59 ocelot->ports[port] = ocelot_port;
60 }
61
62 - if (felix->info->mdio_bus_alloc) {
63 - err = felix->info->mdio_bus_alloc(ocelot);
64 - if (err < 0)
65 - return err;
66 - }
67 -
68 return 0;
69 }
70
71 @@ -384,10 +377,6 @@ static int felix_setup(struct dsa_switch
72 static void felix_teardown(struct dsa_switch *ds)
73 {
74 struct ocelot *ocelot = ds->priv;
75 - struct felix *felix = ocelot_to_felix(ocelot);
76 -
77 - if (felix->imdio)
78 - mdiobus_unregister(felix->imdio);
79
80 /* stop workqueue thread */
81 ocelot_deinit(ocelot);
82 --- a/drivers/net/dsa/ocelot/felix.h
83 +++ b/drivers/net/dsa/ocelot/felix.h
84 @@ -10,7 +10,6 @@
85 struct felix_info {
86 struct resource *target_io_res;
87 struct resource *port_io_res;
88 - struct resource *imdio_res;
89 const struct reg_field *regfields;
90 const u32 *const *map;
91 const struct ocelot_ops *ops;
92 @@ -18,10 +17,8 @@ struct felix_info {
93 const struct ocelot_stat_layout *stats_layout;
94 unsigned int num_stats;
95 int num_ports;
96 - int switch_pci_bar;
97 - int imdio_pci_bar;
98 + int pci_bar;
99 unsigned long quirks;
100 - int (*mdio_bus_alloc)(struct ocelot *ocelot);
101 };
102
103 extern struct felix_info felix_info_vsc9959;
104 @@ -36,8 +33,6 @@ struct felix {
105 struct pci_dev *pdev;
106 struct felix_info *info;
107 struct ocelot ocelot;
108 - struct mii_bus *imdio;
109 - struct phy_device **pcs;
110 };
111
112 #endif
113 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c
114 +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c
115 @@ -2,7 +2,6 @@
116 /* Copyright 2017 Microsemi Corporation
117 * Copyright 2018-2019 NXP Semiconductors
118 */
119 -#include <linux/fsl/enetc_mdio.h>
120 #include <soc/mscc/ocelot_sys.h>
121 #include <soc/mscc/ocelot.h>
122 #include <linux/iopoll.h>
123 @@ -391,15 +390,6 @@ static struct resource vsc9959_port_io_r
124 },
125 };
126
127 -/* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
128 - * SGMII/QSGMII MAC PCS can be found.
129 - */
130 -static struct resource vsc9959_imdio_res = {
131 - .start = 0x8030,
132 - .end = 0x8040,
133 - .name = "imdio",
134 -};
135 -
136 static const struct reg_field vsc9959_regfields[] = {
137 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
138 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
139 @@ -579,291 +569,13 @@ static int vsc9959_reset(struct ocelot *
140 return 0;
141 }
142
143 -void vsc9959_pcs_validate(struct ocelot *ocelot, int port,
144 - unsigned long *supported,
145 - struct phylink_link_state *state)
146 -{
147 - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
148 -
149 - if (state->interface != PHY_INTERFACE_MODE_NA &&
150 - state->interface != PHY_INTERFACE_MODE_GMII &&
151 - state->interface != PHY_INTERFACE_MODE_SGMII &&
152 - state->interface != PHY_INTERFACE_MODE_QSGMII &&
153 - state->interface != PHY_INTERFACE_MODE_USXGMII) {
154 - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
155 - return;
156 - }
157 -
158 - /* No half-duplex. */
159 - phylink_set_port_modes(mask);
160 - phylink_set(mask, Autoneg);
161 - phylink_set(mask, Pause);
162 - phylink_set(mask, Asym_Pause);
163 - phylink_set(mask, 10baseT_Full);
164 - phylink_set(mask, 100baseT_Full);
165 - phylink_set(mask, 1000baseT_Full);
166 - phylink_set(mask, 1000baseX_Full);
167 - phylink_set(mask, 2500baseT_Full);
168 - phylink_set(mask, 2500baseX_Full);
169 - phylink_set(mask, 1000baseKX_Full);
170 -
171 - bitmap_and(supported, supported, mask,
172 - __ETHTOOL_LINK_MODE_MASK_NBITS);
173 - bitmap_and(state->advertising, state->advertising, mask,
174 - __ETHTOOL_LINK_MODE_MASK_NBITS);
175 -}
176 -
177 -static void vsc9959_pcs_an_restart(struct ocelot *ocelot, int port)
178 -{
179 - struct felix *felix = ocelot_to_felix(ocelot);
180 - struct phy_device *pcs = felix->pcs[port];
181 -
182 - if (!pcs)
183 - return;
184 -
185 - phy_set_bits(pcs, MII_BMCR, BMCR_ANRESTART);
186 -}
187 -
188 -static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
189 - unsigned int link_an_mode,
190 - const struct phylink_link_state *state)
191 -{
192 - /* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001
193 - * for the MAC PCS in order to acknowledge the AN.
194 - */
195 - phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII | ADVERTISE_LPACK);
196 -
197 - /* Set to SGMII mode, use AN */
198 - phy_write(pcs, ENETC_PCS_IF_MODE, ENETC_PCS_IF_MODE_SGMII_AN);
199 -
200 - /* Adjust link timer for SGMII */
201 - phy_write(pcs, ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
202 - phy_write(pcs, ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
203 -
204 - phy_write(pcs, MII_BMCR, BMCR_SPEED1000 |
205 - BMCR_FULLDPLX |
206 - BMCR_ANENABLE);
207 -}
208 -
209 -#define ADVERTISE_USXGMII_FDX BIT(12)
210 -
211 -static void vsc9959_pcs_init_sxgmii(struct phy_device *pcs,
212 - unsigned int link_an_mode,
213 - const struct phylink_link_state *state)
214 -{
215 - /* Configure device ability for the USXGMII Replicator */
216 - phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE,
217 - ADVERTISE_SGMII |
218 - ADVERTISE_LPACK |
219 - ADVERTISE_USXGMII_FDX);
220 -}
221 -
222 -static void vsc9959_pcs_init(struct ocelot *ocelot, int port,
223 - unsigned int link_an_mode,
224 - const struct phylink_link_state *state)
225 -{
226 - struct felix *felix = ocelot_to_felix(ocelot);
227 - struct phy_device *pcs = felix->pcs[port];
228 -
229 - if (!pcs)
230 - return;
231 -
232 - if (link_an_mode == MLO_AN_FIXED) {
233 - phydev_err(pcs, "Fixed modes are not yet supported.\n");
234 - return;
235 - }
236 -
237 - pcs->interface = state->interface;
238 - if (pcs->interface == PHY_INTERFACE_MODE_USXGMII)
239 - pcs->is_c45 = true;
240 - else
241 - pcs->is_c45 = false;
242 -
243 - /* The PCS does not implement the BMSR register fully, so capability
244 - * detection via genphy_read_abilities does not work. Since we can get
245 - * the PHY config word from the LPA register though, there is still
246 - * value in using the generic phy_resolve_aneg_linkmode function. So
247 - * populate the supported and advertising link modes manually here.
248 - */
249 - linkmode_set_bit_array(phy_basic_ports_array,
250 - ARRAY_SIZE(phy_basic_ports_array),
251 - pcs->supported);
252 - linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, pcs->supported);
253 - linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported);
254 - linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported);
255 - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported);
256 - phy_advertise_supported(pcs);
257 -
258 - switch (pcs->interface) {
259 - case PHY_INTERFACE_MODE_SGMII:
260 - case PHY_INTERFACE_MODE_QSGMII:
261 - vsc9959_pcs_init_sgmii(pcs, link_an_mode, state);
262 - break;
263 - case PHY_INTERFACE_MODE_USXGMII:
264 - vsc9959_pcs_init_sxgmii(pcs, link_an_mode, state);
265 - break;
266 - default:
267 - dev_err(ocelot->dev, "Unsupported link mode %s\n",
268 - phy_modes(pcs->interface));
269 - }
270 -}
271 -
272 -static void vsc9959_pcs_link_state(struct ocelot *ocelot, int port,
273 - struct phylink_link_state *state)
274 -{
275 - struct felix *felix = ocelot_to_felix(ocelot);
276 - struct phy_device *pcs = felix->pcs[port];
277 - int err;
278 -
279 - if (!pcs)
280 - return;
281 -
282 - /* Reading PCS status not yet supported for USXGMII */
283 - if (pcs->is_c45) {
284 - state->link = 1;
285 - return;
286 - }
287 -
288 - pcs->speed = SPEED_UNKNOWN;
289 - pcs->duplex = DUPLEX_UNKNOWN;
290 - pcs->pause = 0;
291 - pcs->asym_pause = 0;
292 -
293 - err = genphy_update_link(pcs);
294 - if (err < 0)
295 - return;
296 -
297 - if (pcs->autoneg_complete) {
298 - u16 lpa = phy_read(pcs, MII_LPA);
299 -
300 - switch (state->interface) {
301 - case PHY_INTERFACE_MODE_SGMII:
302 - case PHY_INTERFACE_MODE_QSGMII:
303 - mii_lpa_to_linkmode_lpa_sgmii(pcs->lp_advertising, lpa);
304 - break;
305 - default:
306 - return;
307 - }
308 -
309 - phy_resolve_aneg_linkmode(pcs);
310 - }
311 -
312 - state->an_complete = pcs->autoneg_complete;
313 - state->an_enabled = pcs->autoneg;
314 - state->link = pcs->link;
315 - state->duplex = pcs->duplex;
316 - state->speed = pcs->speed;
317 - /* SGMII AN does not negotiate flow control, but that's ok,
318 - * since phylink already knows that, and does:
319 - * link_state.pause |= pl->phy_state.pause;
320 - */
321 - state->pause = pcs->pause;
322 -
323 - dev_dbg(ocelot->dev,
324 - "%s: mode=%s/%s/%s adv=%*pb lpa=%*pb link=%u an_enabled=%u an_complete=%u\n",
325 - __func__,
326 - phy_modes(state->interface),
327 - phy_speed_to_str(state->speed),
328 - phy_duplex_to_str(state->duplex),
329 - __ETHTOOL_LINK_MODE_MASK_NBITS, state->advertising,
330 - __ETHTOOL_LINK_MODE_MASK_NBITS, state->lp_advertising,
331 - state->link, state->an_enabled, state->an_complete);
332 -}
333 -
334 static const struct ocelot_ops vsc9959_ops = {
335 .reset = vsc9959_reset,
336 - .pcs_init = vsc9959_pcs_init,
337 - .pcs_an_restart = vsc9959_pcs_an_restart,
338 - .pcs_link_state = vsc9959_pcs_link_state,
339 - .pcs_validate = vsc9959_pcs_validate,
340 };
341
342 -static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
343 -{
344 - struct felix *felix = ocelot_to_felix(ocelot);
345 - struct enetc_mdio_priv *mdio_priv;
346 - struct device *dev = ocelot->dev;
347 - resource_size_t imdio_base;
348 - void __iomem *imdio_regs;
349 - struct resource *res;
350 - struct enetc_hw *hw;
351 - struct mii_bus *bus;
352 - int port;
353 - int rc;
354 -
355 - felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
356 - sizeof(struct phy_device),
357 - GFP_KERNEL);
358 - if (!felix->pcs) {
359 - dev_err(dev, "failed to allocate array for PCS PHYs\n");
360 - return -ENOMEM;
361 - }
362 -
363 - imdio_base = pci_resource_start(felix->pdev,
364 - felix->info->imdio_pci_bar);
365 -
366 - res = felix->info->imdio_res;
367 - res->flags = IORESOURCE_MEM;
368 - res->start += imdio_base;
369 - res->end += imdio_base;
370 -
371 - imdio_regs = devm_ioremap_resource(dev, res);
372 - if (IS_ERR(imdio_regs)) {
373 - dev_err(dev, "failed to map internal MDIO registers\n");
374 - return PTR_ERR(imdio_regs);
375 - }
376 -
377 - hw = enetc_hw_alloc(dev, imdio_regs);
378 - if (IS_ERR(hw)) {
379 - dev_err(dev, "failed to allocate ENETC HW structure\n");
380 - return PTR_ERR(hw);
381 - }
382 -
383 - bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
384 - if (!bus)
385 - return -ENOMEM;
386 -
387 - bus->name = "VSC9959 internal MDIO bus";
388 - bus->read = enetc_mdio_read;
389 - bus->write = enetc_mdio_write;
390 - bus->parent = dev;
391 - mdio_priv = bus->priv;
392 - mdio_priv->hw = hw;
393 - /* This gets added to imdio_regs, which already maps addresses
394 - * starting with the proper offset.
395 - */
396 - mdio_priv->mdio_base = 0;
397 - snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
398 -
399 - /* Needed in order to initialize the bus mutex lock */
400 - rc = mdiobus_register(bus);
401 - if (rc < 0) {
402 - dev_err(dev, "failed to register MDIO bus\n");
403 - return rc;
404 - }
405 -
406 - felix->imdio = bus;
407 -
408 - for (port = 0; port < felix->info->num_ports; port++) {
409 - struct phy_device *pcs;
410 - bool is_c45 = false;
411 -
412 - pcs = get_phy_device(felix->imdio, port, is_c45);
413 - if (IS_ERR(pcs))
414 - continue;
415 -
416 - felix->pcs[port] = pcs;
417 -
418 - dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
419 - }
420 -
421 - return 0;
422 -}
423 -
424 struct felix_info felix_info_vsc9959 = {
425 .target_io_res = vsc9959_target_io_res,
426 .port_io_res = vsc9959_port_io_res,
427 - .imdio_res = &vsc9959_imdio_res,
428 .regfields = vsc9959_regfields,
429 .map = vsc9959_regmap,
430 .ops = &vsc9959_ops,
431 @@ -871,8 +583,6 @@ struct felix_info felix_info_vsc9959 = {
432 .num_stats = ARRAY_SIZE(vsc9959_stats_layout),
433 .shared_queue_sz = 128 * 1024,
434 .num_ports = 6,
435 - .switch_pci_bar = 4,
436 - .imdio_pci_bar = 0,
437 + .pci_bar = 4,
438 .quirks = OCELOT_PCS_PERFORMS_RATE_ADAPTATION,
439 - .mdio_bus_alloc = vsc9959_mdio_bus_alloc,
440 };
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