git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From ac2bd244609c4423f96406005c9cee8b6952cd20 Mon Sep 17 00:00:00 2001
   2 From: Devi Priya <quic_devipriy@quicinc.com>
   3 Date: Fri, 25 Oct 2024 09:25:16 +0530
   4 Subject: [PATCH 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux
   5  clock
   6
   7 Add support for gpll0_out_aux clock which acts as the parent for
   8 certain networking subsystem (nss) clocks.
   9
  10 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  11 Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
  12 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
  13 ---
  14  drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++
  15  1 file changed, 15 insertions(+)
  16
  17 diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
  18 index 645109f75b46..a458d69e1a98 100644
  19 --- a/drivers/clk/qcom/gcc-ipq9574.c
  20 +++ b/drivers/clk/qcom/gcc-ipq9574.c
  21 @@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 = {
  22         },
  23  };
  24
  25 +static struct clk_alpha_pll_postdiv gpll0_out_aux = {
  26 +       .offset = 0x20000,
  27 +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  28 +       .width = 4,
  29 +       .clkr.hw.init = &(const struct clk_init_data) {
  30 +               .name = "gpll0_out_aux",
  31 +               .parent_hws = (const struct clk_hw *[]) {
  32 +                       &gpll0_main.clkr.hw
  33 +               },
  34 +               .num_parents = 1,
  35 +               .ops = &clk_alpha_pll_postdiv_ro_ops,
  36 +       },
  37 +};
  38 +
  39  static struct clk_alpha_pll gpll4_main = {
  40         .offset = 0x22000,
  41         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
  42 @@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
  43         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
  44         [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
  45         [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
  46 +       [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
  47  };
  48
  49  static const struct qcom_reset_map gcc_ipq9574_resets[] = {
  50 --
  51 2.45.2
  52