git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Fri, 17 Dec 2021 00:03:19 +0800
   4 Subject: [PATCH] ARM: dts: BCM5301X: correct RX delay and enable flow control
   5  on Asus RT-AC88U
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 The current 'rx-internal-delay-ps' property value on the Realtek switch
  11 node, 2000, will be divided by 300, resulting in 6.66, which will be
  12 rounded to the closest step value, 7. Change it to 2100 to be accurate.
  13 See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of
  14 0.3 ns") for reference.
  15
  16 Flow control needs to be enabled on both sides of the internal and
  17 external switch. It is already enabled on the CPU port of the Realtek
  18 switch so we also enable it on the external switch port of the Broadcom
  19 switch as well.
  20
  21 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  22 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  23 ---
  24  arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++-
  25  1 file changed, 2 insertions(+), 1 deletion(-)
  26
  27 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
  28 +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
  29 @@ -138,7 +138,7 @@
  30                                 ethernet = <&sw0_p5>;
  31                                 phy-mode = "rgmii";
  32                                 tx-internal-delay-ps = <2000>;
  33 -                               rx-internal-delay-ps = <2000>;
  34 +                               rx-internal-delay-ps = <2100>;
  35
  36                                 fixed-link {
  37                                         speed = <1000>;
  38 @@ -213,6 +213,7 @@
  39                         fixed-link {
  40                                 speed = <1000>;
  41                                 full-duplex;
  42 +                               pause;
  43                         };
  44                 };
  45