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1 From patchwork Fri Aug 9 16:03:32 2013
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3 MIME-Version: 1.0
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5 Subject: MIPS: add driver for the built-in PCI controller of the RT3883 SoC
6 From: Gabor Juhos <juhosg@openwrt.org>
7 X-Patchwork-Id: 5687
8 Message-Id: <1376064212-28415-1-git-send-email-juhosg@openwrt.org>
9 To: Ralf Baechle <ralf@linux-mips.org>
10 Cc: linux-mips@linux-mips.org, John Crispin <blogic@openwrt.org>,
11 Gabor Juhos <juhosg@openwrt.org>, devicetree@vger.kernel.org
12 Date: Fri, 9 Aug 2013 18:03:32 +0200
13
14 The Ralink RT3883 SoCs have a built-in PCI Host Controller
15 device. The patch adds a platform driver and device tree
16 binding documentation for that.
17
18 The patch also enables the HW_HAS_PCI config option. This
19 is required in order to be able to enable the PCI support.
20
21 Cc: devicetree@vger.kernel.org
22 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
23 Acked-by: John Crispin <blogic@openwrt.org>
24
25 ---
26 .../devicetree/bindings/pci/ralink,rt3883-pci.txt | 169 ++++++
27 arch/mips/pci/Makefile | 1 +
28 arch/mips/pci/pci-rt3883.c | 636 ++++++++++++++++++++
29 arch/mips/ralink/Kconfig | 1 +
30 4 files changed, 807 insertions(+)
31 create mode 100644 Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
32 create mode 100644 arch/mips/pci/pci-rt3883.c
33
34 --- /dev/null
35 +++ b/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
36 @@ -0,0 +1,169 @@
37 +* Mediatek/Ralink RT3883 PCI controller
38 +
39 +1) Main node
40 +
41 + Required properties:
42 +
43 + - compatible: must be "ralink,rt3883-pci"
44 +
45 + - reg: specifies the physical base address of the controller and
46 + the length of the memory mapped region.
47 +
48 + - #address-cells: specifies the number of cells needed to encode an
49 + address. The value must be 1.
50 +
51 + - #size-cells: specifies the number of cells used to represent the size
52 + of an address. The value must be 1.
53 +
54 + - ranges: specifies the translation between child address space and parent
55 + address space
56 +
57 + - status: either "disabled" or "okay"
58 +
59 +2) Child nodes
60 +
61 + The main node must have two child nodes which describes the built-in
62 + interrupt controller and the PCI host bridge.
63 +
64 + a) Interrupt controller:
65 +
66 + Required properties:
67 +
68 + - interrupt-controller: identifies the node as an interrupt controller
69 +
70 + - #address-cells: specifies the number of cells needed to encode an
71 + address. The value must be 0. As such, 'interrupt-map' nodes do not
72 + have to specify a parent unit address.
73 +
74 + - #interrupt-cells: specifies the number of cells needed to encode an
75 + interrupt source. The value must be 1.
76 +
77 + - interrupt-parent: the phandle for the interrupt controller that
78 + services interrupts for this device.
79 +
80 + - interrupts: specifies the interrupt source of the parent interrupt
81 + controller. The format of the interrupt specifier depends on the
82 + parent interrupt controller.
83 +
84 + b) PCI host bridge:
85 +
86 + Required properties:
87 +
88 + - #address-cells: specifies the number of cells needed to encode an
89 + address. The value must be 0.
90 +
91 + - #size-cells: specifies the number of cells used to represent the size
92 + of an address. The value must be 2.
93 +
94 + - #interrupt-cells: specifies the number of cells needed to encode an
95 + interrupt source. The value must be 1.
96 +
97 + - device_type: must be "pci"
98 +
99 + - bus-range: PCI bus numbers covered
100 +
101 + - ranges: specifies the ranges for the PCI memory and I/O regions
102 +
103 + - interrupt-map-mask,
104 + - interrupt-map: standard PCI properties to define the mapping of the
105 + PCI interface to interrupt numbers.
106 +
107 + The PCI host bridge node migh have additional sub-nodes representing
108 + the onboard PCI devices/PCI slots. Each such sub-node must have the
109 + following mandatory properties:
110 +
111 + - reg: used only for interrupt mapping, so only the first four bytes
112 + are used to refer to the correct bus number and device number.
113 +
114 + - device_type: must be "pci"
115 +
116 + - status: either "disabled" or "okay"
117 +
118 + If a given sub-node represents a PCI bridge it must have following
119 + mandatory properties as well:
120 +
121 + - #address-cells: must be set to <3>
122 +
123 + - #size-cells: must set to <2>
124 +
125 + - #interrupt-cells: must be set to <1>
126 +
127 + - interrupt-map-mask,
128 + - interrupt-map: standard PCI properties to define the mapping of the
129 + PCI interface to interrupt numbers.
130 +
131 +3) Example:
132 +
133 + pci@10140000 {
134 + compatible = "ralink,rt3883-pci";
135 + reg = <0x10140000 0x20000>;
136 + #address-cells = <1>;
137 + #size-cells = <1>;
138 + ranges; /* direct mapping */
139 +
140 + status = "disabled";
141 +
142 + pciintc: interrupt-controller {
143 + interrupt-controller;
144 + #address-cells = <0>;
145 + #interrupt-cells = <1>;
146 +
147 + interrupt-parent = <&cpuintc>;
148 + interrupts = <4>;
149 + };
150 +
151 + host-bridge {
152 + #address-cells = <3>;
153 + #size-cells = <2>;
154 + #interrupt-cells = <1>;
155 +
156 + device_type = "pci";
157 +
158 + bus-range = <0 255>;
159 + ranges = <
160 + 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
161 + 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
162 + >;
163 +
164 + interrupt-map-mask = <0xf800 0 0 7>;
165 + interrupt-map = <
166 + /* IDSEL 17 */
167 + 0x8800 0 0 1 &pciintc 18
168 + 0x8800 0 0 2 &pciintc 18
169 + 0x8800 0 0 3 &pciintc 18
170 + 0x8800 0 0 4 &pciintc 18
171 + /* IDSEL 18 */
172 + 0x9000 0 0 1 &pciintc 19
173 + 0x9000 0 0 2 &pciintc 19
174 + 0x9000 0 0 3 &pciintc 19
175 + 0x9000 0 0 4 &pciintc 19
176 + >;
177 +
178 + pci-bridge@1 {
179 + reg = <0x0800 0 0 0 0>;
180 + device_type = "pci";
181 + #interrupt-cells = <1>;
182 + #address-cells = <3>;
183 + #size-cells = <2>;
184 +
185 + interrupt-map-mask = <0x0 0 0 0>;
186 + interrupt-map = <0x0 0 0 0 &pciintc 20>;
187 +
188 + status = "disabled";
189 + };
190 +
191 + pci-slot@17 {
192 + reg = <0x8800 0 0 0 0>;
193 + device_type = "pci";
194 +
195 + status = "disabled";
196 + };
197 +
198 + pci-slot@18 {
199 + reg = <0x9000 0 0 0 0>;
200 + device_type = "pci";
201 +
202 + status = "disabled";
203 + };
204 + };
205 + };
206 --- a/arch/mips/pci/Makefile
207 +++ b/arch/mips/pci/Makefile
208 @@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
209 obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
210 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
211 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
212 +obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
213 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
214 obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
215 obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
216 --- /dev/null
217 +++ b/arch/mips/pci/pci-rt3883.c
218 @@ -0,0 +1,636 @@
219 +/*
220 + * Ralink RT3662/RT3883 SoC PCI support
221 + *
222 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
223 + *
224 + * Parts of this file are based on Ralink's 2.6.21 BSP
225 + *
226 + * This program is free software; you can redistribute it and/or modify it
227 + * under the terms of the GNU General Public License version 2 as published
228 + * by the Free Software Foundation.
229 + */
230 +
231 +#include <linux/types.h>
232 +#include <linux/pci.h>
233 +#include <linux/io.h>
234 +#include <linux/init.h>
235 +#include <linux/delay.h>
236 +#include <linux/interrupt.h>
237 +#include <linux/module.h>
238 +#include <linux/of.h>
239 +#include <linux/of_irq.h>
240 +#include <linux/of_pci.h>
241 +#include <linux/platform_device.h>
242 +
243 +#include <asm/mach-ralink/rt3883.h>
244 +#include <asm/mach-ralink/ralink_regs.h>
245 +
246 +#define RT3883_MEMORY_BASE 0x00000000
247 +#define RT3883_MEMORY_SIZE 0x02000000
248 +
249 +#define RT3883_PCI_REG_PCICFG 0x00
250 +#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
251 +#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
252 +#define RT3883_PCICFG_PCIRST BIT(1)
253 +#define RT3883_PCI_REG_PCIRAW 0x04
254 +#define RT3883_PCI_REG_PCIINT 0x08
255 +#define RT3883_PCI_REG_PCIENA 0x0c
256 +
257 +#define RT3883_PCI_REG_CFGADDR 0x20
258 +#define RT3883_PCI_REG_CFGDATA 0x24
259 +#define RT3883_PCI_REG_MEMBASE 0x28
260 +#define RT3883_PCI_REG_IOBASE 0x2c
261 +#define RT3883_PCI_REG_ARBCTL 0x80
262 +
263 +#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
264 +#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
265 +#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
266 +#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
267 +#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
268 +#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
269 +#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
270 +
271 +#define RT3883_PCI_MODE_NONE 0
272 +#define RT3883_PCI_MODE_PCI BIT(0)
273 +#define RT3883_PCI_MODE_PCIE BIT(1)
274 +#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
275 +
276 +#define RT3883_PCI_IRQ_COUNT 32
277 +
278 +#define RT3883_P2P_BR_DEVNUM 1
279 +
280 +struct rt3883_pci_controller {
281 + void __iomem *base;
282 + spinlock_t lock;
283 +
284 + struct device_node *intc_of_node;
285 + struct irq_domain *irq_domain;
286 +
287 + struct pci_controller pci_controller;
288 + struct resource io_res;
289 + struct resource mem_res;
290 +
291 + bool pcie_ready;
292 +};
293 +
294 +static inline struct rt3883_pci_controller *
295 +pci_bus_to_rt3883_controller(struct pci_bus *bus)
296 +{
297 + struct pci_controller *hose;
298 +
299 + hose = (struct pci_controller *) bus->sysdata;
300 + return container_of(hose, struct rt3883_pci_controller, pci_controller);
301 +}
302 +
303 +static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
304 + unsigned reg)
305 +{
306 + return ioread32(rpc->base + reg);
307 +}
308 +
309 +static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
310 + u32 val, unsigned reg)
311 +{
312 + iowrite32(val, rpc->base + reg);
313 +}
314 +
315 +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
316 + unsigned int func, unsigned int where)
317 +{
318 + return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
319 + 0x80000000;
320 +}
321 +
322 +static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
323 + unsigned bus, unsigned slot,
324 + unsigned func, unsigned reg)
325 +{
326 + unsigned long flags;
327 + u32 address;
328 + u32 ret;
329 +
330 + address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
331 +
332 + spin_lock_irqsave(&rpc->lock, flags);
333 + rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
334 + ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
335 + spin_unlock_irqrestore(&rpc->lock, flags);
336 +
337 + return ret;
338 +}
339 +
340 +static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
341 + unsigned bus, unsigned slot,
342 + unsigned func, unsigned reg, u32 val)
343 +{
344 + unsigned long flags;
345 + u32 address;
346 +
347 + address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
348 +
349 + spin_lock_irqsave(&rpc->lock, flags);
350 + rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
351 + rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
352 + spin_unlock_irqrestore(&rpc->lock, flags);
353 +}
354 +
355 +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
356 +{
357 + struct rt3883_pci_controller *rpc;
358 + u32 pending;
359 +
360 + rpc = irq_get_handler_data(irq);
361 +
362 + pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
363 + rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
364 +
365 + if (!pending) {
366 + spurious_interrupt();
367 + return;
368 + }
369 +
370 + while (pending) {
371 + unsigned bit = __ffs(pending);
372 +
373 + irq = irq_find_mapping(rpc->irq_domain, bit);
374 + generic_handle_irq(irq);
375 +
376 + pending &= ~BIT(bit);
377 + }
378 +}
379 +
380 +static void rt3883_pci_irq_unmask(struct irq_data *d)
381 +{
382 + struct rt3883_pci_controller *rpc;
383 + u32 t;
384 +
385 + rpc = irq_data_get_irq_chip_data(d);
386 +
387 + t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
388 + rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
389 + /* flush write */
390 + rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
391 +}
392 +
393 +static void rt3883_pci_irq_mask(struct irq_data *d)
394 +{
395 + struct rt3883_pci_controller *rpc;
396 + u32 t;
397 +
398 + rpc = irq_data_get_irq_chip_data(d);
399 +
400 + t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
401 + rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
402 + /* flush write */
403 + rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
404 +}
405 +
406 +static struct irq_chip rt3883_pci_irq_chip = {
407 + .name = "RT3883 PCI",
408 + .irq_mask = rt3883_pci_irq_mask,
409 + .irq_unmask = rt3883_pci_irq_unmask,
410 + .irq_mask_ack = rt3883_pci_irq_mask,
411 +};
412 +
413 +static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
414 + irq_hw_number_t hw)
415 +{
416 + irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
417 + irq_set_chip_data(irq, d->host_data);
418 +
419 + return 0;
420 +}
421 +
422 +static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
423 + .map = rt3883_pci_irq_map,
424 + .xlate = irq_domain_xlate_onecell,
425 +};
426 +
427 +static int rt3883_pci_irq_init(struct device *dev,
428 + struct rt3883_pci_controller *rpc)
429 +{
430 + int irq;
431 +
432 + irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
433 + if (irq == 0) {
434 + dev_err(dev, "%s has no IRQ",
435 + of_node_full_name(rpc->intc_of_node));
436 + return -EINVAL;
437 + }
438 +
439 + /* disable all interrupts */
440 + rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
441 +
442 + rpc->irq_domain =
443 + irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
444 + &rt3883_pci_irq_domain_ops,
445 + rpc);
446 + if (!rpc->irq_domain) {
447 + dev_err(dev, "unable to add IRQ domain\n");
448 + return -ENODEV;
449 + }
450 +
451 + irq_set_handler_data(irq, rpc);
452 + irq_set_chained_handler(irq, rt3883_pci_irq_handler);
453 +
454 + return 0;
455 +}
456 +
457 +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
458 + int where, int size, u32 *val)
459 +{
460 + struct rt3883_pci_controller *rpc;
461 + unsigned long flags;
462 + u32 address;
463 + u32 data;
464 +
465 + rpc = pci_bus_to_rt3883_controller(bus);
466 +
467 + if (!rpc->pcie_ready && bus->number == 1)
468 + return PCIBIOS_DEVICE_NOT_FOUND;
469 +
470 + address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
471 + PCI_FUNC(devfn), where);
472 +
473 + spin_lock_irqsave(&rpc->lock, flags);
474 + rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
475 + data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
476 + spin_unlock_irqrestore(&rpc->lock, flags);
477 +
478 + switch (size) {
479 + case 1:
480 + *val = (data >> ((where & 3) << 3)) & 0xff;
481 + break;
482 + case 2:
483 + *val = (data >> ((where & 3) << 3)) & 0xffff;
484 + break;
485 + case 4:
486 + *val = data;
487 + break;
488 + }
489 +
490 + return PCIBIOS_SUCCESSFUL;
491 +}
492 +
493 +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
494 + int where, int size, u32 val)
495 +{
496 + struct rt3883_pci_controller *rpc;
497 + unsigned long flags;
498 + u32 address;
499 + u32 data;
500 +
501 + rpc = pci_bus_to_rt3883_controller(bus);
502 +
503 + if (!rpc->pcie_ready && bus->number == 1)
504 + return PCIBIOS_DEVICE_NOT_FOUND;
505 +
506 + address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
507 + PCI_FUNC(devfn), where);
508 +
509 + spin_lock_irqsave(&rpc->lock, flags);
510 + rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
511 + data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
512 +
513 + switch (size) {
514 + case 1:
515 + data = (data & ~(0xff << ((where & 3) << 3))) |
516 + (val << ((where & 3) << 3));
517 + break;
518 + case 2:
519 + data = (data & ~(0xffff << ((where & 3) << 3))) |
520 + (val << ((where & 3) << 3));
521 + break;
522 + case 4:
523 + data = val;
524 + break;
525 + }
526 +
527 + rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
528 + spin_unlock_irqrestore(&rpc->lock, flags);
529 +
530 + return PCIBIOS_SUCCESSFUL;
531 +}
532 +
533 +static struct pci_ops rt3883_pci_ops = {
534 + .read = rt3883_pci_config_read,
535 + .write = rt3883_pci_config_write,
536 +};
537 +
538 +static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
539 +{
540 + u32 syscfg1;
541 + u32 rstctrl;
542 + u32 clkcfg1;
543 + u32 t;
544 +
545 + rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
546 + syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
547 + clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
548 +
549 + if (mode & RT3883_PCI_MODE_PCIE) {
550 + rstctrl |= RT3883_RSTCTRL_PCIE;
551 + rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
552 +
553 + /* setup PCI PAD drive mode */
554 + syscfg1 &= ~(0x30);
555 + syscfg1 |= (2 << 4);
556 + rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
557 +
558 + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
559 + t &= ~BIT(31);
560 + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
561 +
562 + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
563 + t &= 0x80ffffff;
564 + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
565 +
566 + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
567 + t |= 0xa << 24;
568 + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
569 +
570 + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
571 + t |= BIT(31);
572 + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
573 +
574 + msleep(50);
575 +
576 + rstctrl &= ~RT3883_RSTCTRL_PCIE;
577 + rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
578 + }
579 +
580 + syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
581 +
582 + clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
583 +
584 + if (mode & RT3883_PCI_MODE_PCI) {
585 + clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
586 + rstctrl &= ~RT3883_RSTCTRL_PCI;
587 + }
588 +
589 + if (mode & RT3883_PCI_MODE_PCIE) {
590 + clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
591 + rstctrl &= ~RT3883_RSTCTRL_PCIE;
592 + }
593 +
594 + rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
595 + rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
596 + rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
597 +
598 + msleep(500);
599 +
600 + /*
601 + * setup the device number of the P2P bridge
602 + * and de-assert the reset line
603 + */
604 + t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
605 + rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
606 +
607 + /* flush write */
608 + rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
609 + msleep(500);
610 +
611 + if (mode & RT3883_PCI_MODE_PCIE) {
612 + msleep(500);
613 +
614 + t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
615 +
616 + rpc->pcie_ready = t & BIT(0);
617 +
618 + if (!rpc->pcie_ready) {
619 + /* reset the PCIe block */
620 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
621 + t |= RT3883_RSTCTRL_PCIE;
622 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
623 + t &= ~RT3883_RSTCTRL_PCIE;
624 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
625 +
626 + /* turn off PCIe clock */
627 + t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
628 + t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
629 + rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
630 +
631 + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
632 + t &= ~0xf000c080;
633 + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
634 + }
635 + }
636 +
637 + /* enable PCI arbiter */
638 + rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
639 +}
640 +
641 +static int rt3883_pci_probe(struct platform_device *pdev)
642 +{
643 + struct rt3883_pci_controller *rpc;
644 + struct device *dev = &pdev->dev;
645 + struct device_node *np = dev->of_node;
646 + struct resource *res;
647 + struct device_node *child;
648 + u32 val;
649 + int err;
650 + int mode;
651 +
652 + rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
653 + if (!rpc)
654 + return -ENOMEM;
655 +
656 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
657 + if (!res)
658 + return -EINVAL;
659 +
660 + rpc->base = devm_ioremap_resource(dev, res);
661 + if (IS_ERR(rpc->base))
662 + return PTR_ERR(rpc->base);
663 +
664 + /* find the interrupt controller child node */
665 + for_each_child_of_node(np, child) {
666 + if (of_get_property(child, "interrupt-controller", NULL) &&
667 + of_node_get(child)) {
668 + rpc->intc_of_node = child;
669 + break;
670 + }
671 + }
672 +
673 + if (!rpc->intc_of_node) {
674 + dev_err(dev, "% has no %s child node",
675 + of_node_full_name(rpc->intc_of_node),
676 + "interrupt controller");
677 + return -EINVAL;
678 + }
679 +
680 + /* find the PCI host bridge child node */
681 + for_each_child_of_node(np, child) {
682 + if (child->type &&
683 + of_node_cmp(child->type, "pci") == 0 &&
684 + of_node_get(child)) {
685 + rpc->pci_controller.of_node = child;
686 + break;
687 + }
688 + }
689 +
690 + if (!rpc->pci_controller.of_node) {
691 + dev_err(dev, "%s has no %s child node",
692 + of_node_full_name(rpc->intc_of_node),
693 + "PCI host bridge");
694 + err = -EINVAL;
695 + goto err_put_intc_node;
696 + }
697 +
698 + mode = RT3883_PCI_MODE_NONE;
699 + for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
700 + int devfn;
701 +
702 + if (!child->type ||
703 + of_node_cmp(child->type, "pci") != 0)
704 + continue;
705 +
706 + devfn = of_pci_get_devfn(child);
707 + if (devfn < 0)
708 + continue;
709 +
710 + switch (PCI_SLOT(devfn)) {
711 + case 1:
712 + mode |= RT3883_PCI_MODE_PCIE;
713 + break;
714 +
715 + case 17:
716 + case 18:
717 + mode |= RT3883_PCI_MODE_PCI;
718 + break;
719 + }
720 + }
721 +
722 + if (mode == RT3883_PCI_MODE_NONE) {
723 + dev_err(dev, "unable to determine PCI mode\n");
724 + err = -EINVAL;
725 + goto err_put_hb_node;
726 + }
727 +
728 + dev_info(dev, "mode:%s%s\n",
729 + (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
730 + (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
731 +
732 + rt3883_pci_preinit(rpc, mode);
733 +
734 + rpc->pci_controller.pci_ops = &rt3883_pci_ops;
735 + rpc->pci_controller.io_resource = &rpc->io_res;
736 + rpc->pci_controller.mem_resource = &rpc->mem_res;
737 +
738 + /* Load PCI I/O and memory resources from DT */
739 + pci_load_of_ranges(&rpc->pci_controller,
740 + rpc->pci_controller.of_node);
741 +
742 + rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
743 + rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
744 +
745 + ioport_resource.start = rpc->io_res.start;
746 + ioport_resource.end = rpc->io_res.end;
747 +
748 + /* PCI */
749 + rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
750 + rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
751 + rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
752 + rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
753 + rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
754 +
755 + /* PCIe */
756 + rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
757 + rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
758 + rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
759 + rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
760 + rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
761 +
762 + err = rt3883_pci_irq_init(dev, rpc);
763 + if (err)
764 + goto err_put_hb_node;
765 +
766 + /* PCIe */
767 + val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
768 + val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
769 + rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
770 +
771 + /* PCI */
772 + val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
773 + val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
774 + rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
775 +
776 + if (mode == RT3883_PCI_MODE_PCIE) {
777 + rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
778 + rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
779 +
780 + rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
781 + PCI_BASE_ADDRESS_0,
782 + RT3883_MEMORY_BASE);
783 + /* flush write */
784 + rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
785 + PCI_BASE_ADDRESS_0);
786 + } else {
787 + rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
788 + PCI_IO_BASE, 0x00000101);
789 + }
790 +
791 + register_pci_controller(&rpc->pci_controller);
792 +
793 + return 0;
794 +
795 +err_put_hb_node:
796 + of_node_put(rpc->pci_controller.of_node);
797 +err_put_intc_node:
798 + of_node_put(rpc->intc_of_node);
799 + return err;
800 +}
801 +
802 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
803 +{
804 + struct of_irq dev_irq;
805 + int err;
806 + int irq;
807 +
808 + err = of_irq_map_pci(dev, &dev_irq);
809 + if (err) {
810 + pr_err("pci %s: unable to get irq map, err=%d\n",
811 + pci_name((struct pci_dev *) dev), err);
812 + return 0;
813 + }
814 +
815 + irq = irq_create_of_mapping(dev_irq.controller,
816 + dev_irq.specifier,
817 + dev_irq.size);
818 +
819 + if (irq == 0)
820 + pr_crit("pci %s: no irq found for pin %u\n",
821 + pci_name((struct pci_dev *) dev), pin);
822 + else
823 + pr_info("pci %s: using irq %d for pin %u\n",
824 + pci_name((struct pci_dev *) dev), irq, pin);
825 +
826 + return irq;
827 +}
828 +
829 +int pcibios_plat_dev_init(struct pci_dev *dev)
830 +{
831 + return 0;
832 +}
833 +
834 +static const struct of_device_id rt3883_pci_ids[] = {
835 + { .compatible = "ralink,rt3883-pci" },
836 + {},
837 +};
838 +MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
839 +
840 +static struct platform_driver rt3883_pci_driver = {
841 + .probe = rt3883_pci_probe,
842 + .driver = {
843 + .name = "rt3883-pci",
844 + .owner = THIS_MODULE,
845 + .of_match_table = of_match_ptr(rt3883_pci_ids),
846 + },
847 +};
848 +
849 +static int __init rt3883_pci_init(void)
850 +{
851 + return platform_driver_register(&rt3883_pci_driver);
852 +}
853 +
854 +postcore_initcall(rt3883_pci_init);
855 --- a/arch/mips/ralink/Kconfig
856 +++ b/arch/mips/ralink/Kconfig
857 @@ -26,6 +26,7 @@ choice
858 bool "RT3883"
859 select USB_ARCH_HAS_OHCI
860 select USB_ARCH_HAS_EHCI
861 + select HW_HAS_PCI
862
863 config SOC_MT7620
864 bool "MT7620"