git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From bab2f1e4e90675af7ea6b48b5c28eb94e22cecd7 Mon Sep 17 00:00:00 2001
   2 From: Jonathan Bell <jonathan@raspberrypi.com>
   3 Date: Thu, 13 Jul 2023 15:06:54 +0100
   4 Subject: [PATCH 0483/1085] usb: xhci: borrow upstream TRB_FETCH quirk on VL805
   5  hosts
   6
   7 This reimplements 5a57342 usb: xhci: add VLI_TRB_CACHE_BUG quirk
   8
   9 The downstream implementation required a fair bit of driver surgery to
  10 allow for truncated ring segments, which needed to shrink by a small
  11 amount to avoid the cache prefetcher from reading off the end of one
  12 segment and into another.
  13
  14 An upstream implementation for a similar bug on a different controller
  15 just doubles the size of the memory allocated for ring segments, which
  16 is a bit more wasteful (+4K per allocation) but means less code churn.
  17
  18 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  19 ---
  20  drivers/usb/host/xhci-pci.c | 1 +
  21  1 file changed, 1 insertion(+)
  22
  23 --- a/drivers/usb/host/xhci-pci.c
  24 +++ b/drivers/usb/host/xhci-pci.c
  25 @@ -494,6 +494,7 @@ static void xhci_pci_quirks(struct devic
  26                 xhci->quirks |= XHCI_LPM_SUPPORT;
  27                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
  28                 xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
  29 +               xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
  30         }
  31
  32         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&