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1 From e0c82f36ad5180d9582d353407ff1bf34a2734bb Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 20 May 2022 11:22:21 +0800
4 Subject: [PATCH 05/25] mips: mtmips: add support for MediaTek MT7621 SoC
5
6 This patch adds support for MediaTek MT7621 SoC.
7 All files are dedicated for u-boot.
8
9 The default build target is u-boot-mt7621.bin.
10
11 The specification of this chip:
12 https://www.mediatek.com/products/homenetworking/mt7621
13
14 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
15 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
16 ---
17 arch/mips/dts/mt7621-u-boot.dtsi | 111 ++++++
18 arch/mips/dts/mt7621.dtsi | 349 +++++++++++++++++++
19 arch/mips/mach-mtmips/Kconfig | 49 ++-
20 arch/mips/mach-mtmips/Makefile | 4 +
21 arch/mips/mach-mtmips/cpu.c | 2 +-
22 arch/mips/mach-mtmips/mt7621/Kconfig | 95 +++++
23 arch/mips/mach-mtmips/mt7621/Makefile | 14 +
24 arch/mips/mach-mtmips/mt7621/init.c | 246 +++++++++++++
25 arch/mips/mach-mtmips/mt7621/mt7621.h | 229 ++++++++++++
26 arch/mips/mach-mtmips/mt7621/serial.c | 23 ++
27 arch/mips/mach-mtmips/mt7621/spl/Makefile | 9 +
28 arch/mips/mach-mtmips/mt7621/spl/cps.c | 153 ++++++++
29 arch/mips/mach-mtmips/mt7621/spl/dram.c | 153 ++++++++
30 arch/mips/mach-mtmips/mt7621/spl/dram.h | 39 +++
31 arch/mips/mach-mtmips/mt7621/spl/launch.c | 100 ++++++
32 arch/mips/mach-mtmips/mt7621/spl/launch.h | 52 +++
33 arch/mips/mach-mtmips/mt7621/spl/launch_ll.S | 339 ++++++++++++++++++
34 arch/mips/mach-mtmips/mt7621/spl/serial.c | 24 ++
35 arch/mips/mach-mtmips/mt7621/spl/spl.c | 95 +++++
36 arch/mips/mach-mtmips/mt7621/spl/start.S | 226 ++++++++++++
37 arch/mips/mach-mtmips/mt7621/sram_init.S | 22 ++
38 arch/mips/mach-mtmips/mt7621/tpl/Makefile | 4 +
39 arch/mips/mach-mtmips/mt7621/tpl/start.S | 161 +++++++++
40 arch/mips/mach-mtmips/mt7621/tpl/tpl.c | 144 ++++++++
41 include/configs/mt7621.h | 65 ++++
42 25 files changed, 2702 insertions(+), 6 deletions(-)
43 create mode 100644 arch/mips/dts/mt7621-u-boot.dtsi
44 create mode 100644 arch/mips/dts/mt7621.dtsi
45 create mode 100644 arch/mips/mach-mtmips/mt7621/Kconfig
46 create mode 100644 arch/mips/mach-mtmips/mt7621/Makefile
47 create mode 100644 arch/mips/mach-mtmips/mt7621/init.c
48 create mode 100644 arch/mips/mach-mtmips/mt7621/mt7621.h
49 create mode 100644 arch/mips/mach-mtmips/mt7621/serial.c
50 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/Makefile
51 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/cps.c
52 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/dram.c
53 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/dram.h
54 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch.c
55 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch.h
56 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch_ll.S
57 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/serial.c
58 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/spl.c
59 create mode 100644 arch/mips/mach-mtmips/mt7621/spl/start.S
60 create mode 100644 arch/mips/mach-mtmips/mt7621/sram_init.S
61 create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/Makefile
62 create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/start.S
63 create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/tpl.c
64 create mode 100644 include/configs/mt7621.h
65
66 --- /dev/null
67 +++ b/arch/mips/dts/mt7621-u-boot.dtsi
68 @@ -0,0 +1,111 @@
69 +// SPDX-License-Identifier: GPL-2.0
70 +/*
71 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
72 + *
73 + * Author: Weijie Gao <weijie.gao@mediatek.com>
74 + */
75 +
76 +#include <linux/stringify.h>
77 +
78 +/ {
79 + binman: binman {
80 + multiple-images;
81 + };
82 +};
83 +
84 +&sysc {
85 + u-boot,dm-pre-reloc;
86 +};
87 +
88 +&reboot {
89 + u-boot,dm-pre-reloc;
90 +};
91 +
92 +&clkctrl {
93 + u-boot,dm-pre-reloc;
94 +};
95 +
96 +&rstctrl {
97 + u-boot,dm-pre-reloc;
98 +};
99 +
100 +&pinctrl {
101 + u-boot,dm-pre-reloc;
102 +};
103 +
104 +&uart0 {
105 + u-boot,dm-pre-reloc;
106 +};
107 +
108 +&uart1 {
109 + u-boot,dm-pre-reloc;
110 +};
111 +
112 +&uart2 {
113 + u-boot,dm-pre-reloc;
114 +};
115 +
116 +&binman {
117 + u-boot-spl-ddr {
118 + align = <4>;
119 + align-size = <4>;
120 + filename = "u-boot-spl-ddr.bin";
121 + pad-byte = <0xff>;
122 +
123 + u-boot-spl {
124 + align-end = <4>;
125 + filename = "u-boot-spl.bin";
126 + };
127 +
128 + stage_bin {
129 + filename = "mt7621_stage_sram.bin";
130 + type = "blob-ext";
131 + };
132 + };
133 +
134 + spl-img {
135 + filename = "u-boot-spl-ddr.img";
136 +
137 + mkimage {
138 +#ifdef CONFIG_MT7621_BOOT_FROM_NAND
139 + args = "-T", "mtk_image", "-n", "mt7621=1",
140 + "-a", __stringify(CONFIG_SPL_TEXT_BASE),
141 + "-e", __stringify(CONFIG_SPL_TEXT_BASE);
142 +#else
143 + args = "-A", "mips", "-T", "standalone", "-O", "u-boot",
144 + "-C", "none", "-n", "MT7621 U-Boot SPL",
145 + "-a", __stringify(CONFIG_SPL_TEXT_BASE),
146 + "-e", __stringify(CONFIG_SPL_TEXT_BASE);
147 +#endif
148 +
149 + blob {
150 + filename = "u-boot-spl-ddr.bin";
151 + };
152 + };
153 + };
154 +
155 + mt7621-uboot {
156 + filename = "u-boot-mt7621.bin";
157 + pad-byte = <0xff>;
158 +
159 +#ifndef CONFIG_MT7621_BOOT_FROM_NAND
160 + u-boot-tpl {
161 + align-end = <4>;
162 + filename = "u-boot-tpl.bin";
163 + };
164 +#endif
165 +
166 + spl {
167 +#ifdef CONFIG_MT7621_BOOT_FROM_NAND
168 + align-end = <0x1000>;
169 +#endif
170 + filename = "u-boot-spl-ddr.img";
171 + type = "blob";
172 + };
173 +
174 + u-boot {
175 + filename = "u-boot-lzma.img";
176 + type = "blob";
177 + };
178 + };
179 +};
180 --- /dev/null
181 +++ b/arch/mips/dts/mt7621.dtsi
182 @@ -0,0 +1,349 @@
183 +// SPDX-License-Identifier: GPL-2.0
184 +/*
185 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
186 + *
187 + * Author: Weijie Gao <weijie.gao@mediatek.com>
188 + */
189 +
190 +#include <dt-bindings/clock/mt7621-clk.h>
191 +#include <dt-bindings/reset/mt7621-reset.h>
192 +#include <dt-bindings/phy/phy.h>
193 +
194 +/ {
195 + #address-cells = <1>;
196 + #size-cells = <1>;
197 + compatible = "mediatek,mt7621-soc";
198 +
199 + cpus {
200 + #address-cells = <1>;
201 + #size-cells = <0>;
202 +
203 + cpu@0 {
204 + device_type = "cpu";
205 + compatible = "mips,mips1004Kc";
206 + reg = <0>;
207 + };
208 +
209 + cpu@1 {
210 + device_type = "cpu";
211 + compatible = "mips,mips1004Kc";
212 + reg = <1>;
213 + };
214 + };
215 +
216 + clk48m: clk48m {
217 + compatible = "fixed-clock";
218 +
219 + clock-frequency = <48000000>;
220 +
221 + #clock-cells = <0>;
222 + };
223 +
224 + clk50m: clk50m {
225 + compatible = "fixed-clock";
226 +
227 + clock-frequency = <50000000>;
228 +
229 + #clock-cells = <0>;
230 + };
231 +
232 + sysc: sysctrl@1e000000 {
233 + compatible = "mediatek,mt7621-sysc", "syscon";
234 + reg = <0x1e000000 0x100>;
235 +
236 + clkctrl: clock-controller@1e000030 {
237 + compatible = "mediatek,mt7621-clk";
238 + mediatek,memc = <&memc>;
239 +
240 + #clock-cells = <1>;
241 + };
242 + };
243 +
244 + rstctrl: reset-controller@1e000034 {
245 + compatible = "mediatek,mtmips-reset";
246 + reg = <0x1e000034 0x4>;
247 + #reset-cells = <1>;
248 + };
249 +
250 + reboot: resetctl-reboot {
251 + compatible = "resetctl-reboot";
252 +
253 + resets = <&rstctrl RST_SYS>;
254 + reset-names = "sysreset";
255 + };
256 +
257 + memc: memctrl@1e005000 {
258 + compatible = "mediatek,mt7621-memc", "syscon";
259 + reg = <0x1e005000 0x1000>;
260 + };
261 +
262 + pinctrl: pinctrl@1e000060 {
263 + compatible = "mediatek,mt7621-pinctrl";
264 + reg = <0x1e000048 0x30>;
265 +
266 + pinctrl-names = "default";
267 + pinctrl-0 = <&state_default>;
268 +
269 + state_default: pin_state {
270 + };
271 +
272 + uart1_pins: uart1_pins {
273 + groups = "uart1";
274 + function = "uart";
275 + };
276 +
277 + uart2_pins: uart2_pins {
278 + groups = "uart2";
279 + function = "uart";
280 + };
281 +
282 + uart3_pins: uart3_pins {
283 + groups = "uart3";
284 + function = "uart";
285 + };
286 +
287 + sdxc_pins: sdxc_pins {
288 + groups = "sdxc";
289 + function = "sdxc";
290 + };
291 +
292 + spi_pins: spi_pins {
293 + groups = "spi";
294 + function = "spi";
295 + };
296 +
297 + eth_pins: eth_pins {
298 + mdio_pins {
299 + groups = "mdio";
300 + function = "mdio";
301 + };
302 +
303 + rgmii1_pins {
304 + groups = "rgmii1";
305 + function = "rgmii";
306 + };
307 +
308 + esw_pins {
309 + groups = "esw int";
310 + function = "esw int";
311 + };
312 +
313 + mdio_pconf {
314 + groups = "mdio";
315 + drive-strength = <2>;
316 + };
317 + };
318 + };
319 +
320 + watchdog: watchdog@1e000100 {
321 + compatible = "mediatek,mt7621-wdt";
322 + reg = <0x1e000100 0x40>;
323 +
324 + resets = <&rstctrl RST_TIMER>;
325 + reset-names = "wdt";
326 +
327 + status = "disabled";
328 + };
329 +
330 + gpio: gpio@1e000600 {
331 + #address-cells = <1>;
332 + #size-cells = <0>;
333 +
334 + compatible = "mtk,mt7621-gpio";
335 + reg = <0x1e000600 0x100>;
336 +
337 + resets = <&rstctrl RST_PIO>;
338 + reset-names = "pio";
339 +
340 + gpio0: bank@0 {
341 + reg = <0>;
342 + compatible = "mtk,mt7621-gpio-bank";
343 + gpio-controller;
344 + #gpio-cells = <2>;
345 + };
346 +
347 + gpio1: bank@1 {
348 + reg = <1>;
349 + compatible = "mtk,mt7621-gpio-bank";
350 + gpio-controller;
351 + #gpio-cells = <2>;
352 + };
353 +
354 + gpio2: bank@2 {
355 + reg = <2>;
356 + compatible = "mtk,mt7621-gpio-bank";
357 + gpio-controller;
358 + #gpio-cells = <2>;
359 + };
360 + };
361 +
362 + spi: spi@1e000b00 {
363 + compatible = "ralink,mt7621-spi";
364 + reg = <0x1e000b00 0x40>;
365 +
366 + status = "disabled";
367 +
368 + pinctrl-names = "default";
369 + pinctrl-0 = <&spi_pins>;
370 +
371 + resets = <&rstctrl RST_SPI>;
372 + reset-names = "spi";
373 +
374 + clocks = <&clkctrl MT7621_CLK_SPI>;
375 +
376 + #address-cells = <1>;
377 + #size-cells = <0>;
378 + };
379 +
380 + uart0: uart1@1e000c00 {
381 + compatible = "mediatek,hsuart", "ns16550a";
382 + reg = <0x1e000c00 0x100>;
383 +
384 + pinctrl-names = "default";
385 + pinctrl-0 = <&uart1_pins>;
386 +
387 + clocks = <&clkctrl MT7621_CLK_UART1>;
388 +
389 + resets = <&rstctrl RST_UART1>;
390 +
391 + reg-shift = <2>;
392 + };
393 +
394 + uart1: uart2@1e000d00 {
395 + compatible = "mediatek,hsuart", "ns16550a";
396 + reg = <0x1e000d00 0x100>;
397 +
398 + pinctrl-names = "default";
399 + pinctrl-0 = <&uart2_pins>;
400 +
401 + clocks = <&clkctrl MT7621_CLK_UART2>;
402 +
403 + resets = <&rstctrl RST_UART2>;
404 +
405 + reg-shift = <2>;
406 +
407 + status = "disabled";
408 + };
409 +
410 + uart2: uart3@1e000e00 {
411 + compatible = "mediatek,hsuart", "ns16550a";
412 + reg = <0x1e000e00 0x100>;
413 +
414 + pinctrl-names = "default";
415 + pinctrl-0 = <&uart3_pins>;
416 +
417 + clocks = <&clkctrl MT7621_CLK_UART3>;
418 +
419 + resets = <&rstctrl RST_UART3>;
420 +
421 + reg-shift = <2>;
422 +
423 + status = "disabled";
424 + };
425 +
426 + eth: eth@1e100000 {
427 + compatible = "mediatek,mt7621-eth";
428 + reg = <0x1e100000 0x20000>;
429 + mediatek,ethsys = <&sysc>;
430 +
431 + pinctrl-names = "default";
432 + pinctrl-0 = <&eth_pins>;
433 +
434 + resets = <&rstctrl RST_FE>, <&rstctrl RST_GMAC>, <&rstctrl RST_MCM>;
435 + reset-names = "fe", "gmac", "mcm";
436 +
437 + clocks = <&clkctrl MT7621_CLK_GDMA>,
438 + <&clkctrl MT7621_CLK_ETH>;
439 + clock-names = "gmac", "fe";
440 +
441 + #address-cells = <1>;
442 + #size-cells = <0>;
443 +
444 + mediatek,gmac-id = <0>;
445 + phy-mode = "rgmii";
446 + mediatek,switch = "mt7530";
447 + mediatek,mcm;
448 +
449 + fixed-link {
450 + speed = <1000>;
451 + full-duplex;
452 + };
453 + };
454 +
455 + mmc: mmc@1e130000 {
456 + compatible = "mediatek,mt7621-mmc";
457 + reg = <0x1e130000 0x4000>;
458 +
459 + status = "disabled";
460 +
461 + bus-width = <4>;
462 + builtin-cd = <1>;
463 + r_smpl = <1>;
464 +
465 + pinctrl-names = "default";
466 + pinctrl-0 = <&sdxc_pins>;
467 +
468 + clocks = <&clk50m>, <&clkctrl MT7621_CLK_SHXC>;
469 + clock-names = "source", "hclk";
470 +
471 + resets = <&rstctrl RST_SDXC>;
472 + };
473 +
474 + ssusb: usb@1e1c0000 {
475 + compatible = "mediatek,mt7621-xhci", "mediatek,mtk-xhci";
476 + reg = <0x1e1c0000 0x1000>, <0x1e1d0700 0x100>;
477 + reg-names = "mac", "ippc";
478 +
479 + clocks = <&clk48m>, <&clk48m>;
480 + clock-names = "sys_ck", "ref_ck";
481 +
482 + phys = <&u2port0 PHY_TYPE_USB2>,
483 + <&u3port0 PHY_TYPE_USB3>,
484 + <&u2port1 PHY_TYPE_USB2>;
485 +
486 + status = "disabled";
487 + };
488 +
489 + u3phy: usb-phy@1e1d0000 {
490 + compatible = "mediatek,mt7621-u3phy",
491 + "mediatek,generic-tphy-v1";
492 + reg = <0x1e1d0000 0x700>;
493 + #address-cells = <1>;
494 + #size-cells = <1>;
495 + ranges;
496 + status = "disabled";
497 +
498 + u2port0: usb-phy@1e1d0800 {
499 + reg = <0x1e1d0800 0x0100>;
500 + #phy-cells = <1>;
501 + clocks = <&clk48m>;
502 + clock-names = "ref";
503 + };
504 +
505 + u3port0: usb-phy@1e1d0900 {
506 + reg = <0x1e1d0900 0x0100>;
507 + #phy-cells = <1>;
508 + };
509 +
510 + u2port1: usb-phy@1e1d1000 {
511 + reg = <0x1e1d1000 0x0100>;
512 + #phy-cells = <1>;
513 + clocks = <&clk48m>;
514 + clock-names = "ref";
515 + };
516 + };
517 +
518 + i2c: i2c@1e000900 {
519 + compatible = "i2c-gpio";
520 +
521 + status = "disabled";
522 +
523 + i2c-gpio,delay-us = <3>;
524 +
525 + gpios = <&gpio0 3 1>, /* PIN3 as SDA */
526 + <&gpio0 4 1>; /* PIN4 as CLK */
527 +
528 + #address-cells = <1>;
529 + #size-cells = <0>;
530 + };
531 +};
532 --- a/arch/mips/mach-mtmips/Kconfig
533 +++ b/arch/mips/mach-mtmips/Kconfig
534 @@ -9,6 +9,7 @@ config SYS_MALLOC_F_LEN
535
536 config SYS_SOC
537 default "mt7620" if SOC_MT7620
538 + default "mt7621" if SOC_MT7621
539 default "mt7628" if SOC_MT7628
540
541 config SYS_DCACHE_SIZE
542 @@ -18,25 +19,45 @@ config SYS_DCACHE_LINE_SIZE
543 default 32
544
545 config SYS_ICACHE_SIZE
546 - default 65536
547 + default 65536 if SOC_MT7620 || SOC_MT7628
548 + default 32768 if SOC_MT7621
549
550 config SYS_ICACHE_LINE_SIZE
551 default 32
552
553 +config SYS_SCACHE_LINE_SIZE
554 + default 32 if SOC_MT7621
555 +
556 config SYS_TEXT_BASE
557 - default 0x9c000000 if !SPL
558 - default 0x80200000 if SPL
559 + default 0x9c000000 if !SPL && !SOC_MT7621
560 + default 0x80200000 if SPL || SOC_MT7621
561
562 config SPL_TEXT_BASE
563 - default 0x9c000000
564 + default 0x9c000000 if !SOC_MT7621
565 + default 0x80100000 if SOC_MT7621
566 +
567 +config SPL_SIZE_LIMIT
568 + default 0x30000 if SOC_MT7621
569 +
570 +config TPL_TEXT_BASE
571 + default 0xbfc00000 if SOC_MT7621
572 +
573 +config TPL_MAX_SIZE
574 + default 4096 if SOC_MT7621
575
576 config SPL_PAYLOAD
577 default "u-boot-lzma.img" if SPL_LZMA
578
579 config BUILD_TARGET
580 - default "u-boot-with-spl.bin" if SPL
581 + default "u-boot-with-spl.bin" if SPL && !SOC_MT7621
582 + default "u-boot-lzma.img" if SOC_MT7621
583 default "u-boot.bin"
584
585 +config MAX_MEM_SIZE
586 + int
587 + default 256 if SOC_MT7620 || SOC_MT7628
588 + default 512 if SOC_MT7621
589 +
590 choice
591 prompt "MediaTek MIPS SoC select"
592
593 @@ -55,6 +76,23 @@ config SOC_MT7620
594 help
595 This supports MediaTek MT7620.
596
597 +config SOC_MT7621
598 + bool "MT7621"
599 + select MIPS_CM
600 + select MIPS_L2_CACHE
601 + select SYS_CACHE_SHIFT_5
602 + select SYS_MIPS_CACHE_INIT_RAM_LOAD
603 + select PINCTRL_MT7621
604 + select MTK_SERIAL
605 + select REGMAP
606 + select SYSCON
607 + select BINMAN
608 + select SUPPORT_TPL
609 + select SPL_LOADER_SUPPORT if SPL
610 + select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
611 + help
612 + This supports MediaTek MT7621.
613 +
614 config SOC_MT7628
615 bool "MT7628"
616 select SYS_CACHE_SHIFT_5
617 @@ -80,6 +118,7 @@ config SOC_MT7628
618 endchoice
619
620 source "arch/mips/mach-mtmips/mt7620/Kconfig"
621 +source "arch/mips/mach-mtmips/mt7621/Kconfig"
622 source "arch/mips/mach-mtmips/mt7628/Kconfig"
623
624 endmenu
625 --- a/arch/mips/mach-mtmips/Makefile
626 +++ b/arch/mips/mach-mtmips/Makefile
627 @@ -1,9 +1,13 @@
628 # SPDX-License-Identifier: GPL-2.0+
629
630 obj-y += cpu.o
631 +
632 +ifneq ($(CONFIG_SOC_MT7621),y)
633 obj-y += ddr_init.o
634 obj-y += ddr_cal.o
635 obj-$(CONFIG_SPL_BUILD) += spl.o
636 +endif
637
638 obj-$(CONFIG_SOC_MT7620) += mt7620/
639 +obj-$(CONFIG_SOC_MT7621) += mt7621/
640 obj-$(CONFIG_SOC_MT7628) += mt7628/
641 --- a/arch/mips/mach-mtmips/cpu.c
642 +++ b/arch/mips/mach-mtmips/cpu.c
643 @@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
644
645 int dram_init(void)
646 {
647 - gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
648 + gd->ram_size = get_ram_size((void *)KSEG1, CONFIG_MAX_MEM_SIZE << 20);
649
650 return 0;
651 }
652 --- /dev/null
653 +++ b/arch/mips/mach-mtmips/mt7621/Kconfig
654 @@ -0,0 +1,95 @@
655 +
656 +if SOC_MT7621
657 +
658 +menu "CPU & DDR configuration"
659 +
660 +config MT7621_CPU_FREQ
661 + int "CPU Frequency (MHz)"
662 + range 400 1200
663 + default 880
664 +
665 +choice
666 + prompt "DRAM Frequency"
667 + default MT7621_DRAM_FREQ_1200
668 +
669 +config MT7621_DRAM_FREQ_400
670 + bool "400MHz"
671 +
672 +config MT7621_DRAM_FREQ_800
673 + bool "800MHz"
674 +
675 +config MT7621_DRAM_FREQ_1066
676 + bool "1066MHz"
677 +
678 +config MT7621_DRAM_FREQ_1200
679 + bool "1200MHz"
680 +
681 +endchoice
682 +
683 +choice
684 + prompt "DDR2 timing parameters"
685 + default MT7621_DRAM_DDR2_1024M
686 +
687 +config MT7621_DRAM_DDR2_512M
688 + bool "64MB"
689 +
690 +config MT7621_DRAM_DDR2_1024M
691 + bool "128MB"
692 +
693 +config MT7621_DRAM_DDR2_512M_W9751G6KB_A02_1066MHZ
694 + bool "W9751G6KB_A02 @ 1066MHz (64MB)"
695 +
696 +config MT7621_DRAM_DDR2_1024M_W971GG6KB25_800MHZ
697 + bool "W971GG6KB25 @ 800MHz (128MB)"
698 +
699 +config MT7621_DRAM_DDR2_1024M_W971GG6KB18_1066MHZ
700 + bool "W971GG6KB18 @ 1066MHz (128MB)"
701 +
702 +endchoice
703 +
704 +choice
705 + prompt "DDR3 timing parameters"
706 + default MT7621_DRAM_DDR3_2048M
707 +
708 +config MT7621_DRAM_DDR3_1024M
709 + bool "128MB"
710 +
711 +config MT7621_DRAM_DDR3_1024M_KGD
712 + bool "128MB KGD (MT7621DA)"
713 +
714 +config MT7621_DRAM_DDR3_2048M
715 + bool "256MB"
716 +
717 +config MT7621_DRAM_DDR3_4096M
718 + bool "512MB"
719 +
720 +endchoice
721 +
722 +endmenu
723 +
724 +config DEBUG_UART_BOARD_INIT
725 + default y
726 +
727 +config MT7621_BOOT_FROM_NAND
728 + bool "Boot from NAND"
729 + help
730 + Select this if u-boot will boot from NAND flash. When booting from
731 + NAND, SPL will be loaded by bootrom directly and no TPL is needed.
732 +
733 +choice
734 + prompt "Board select"
735 +
736 +endchoice
737 +
738 +config SYS_CONFIG_NAME
739 + string "Board configuration name"
740 + default "mt7621" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB
741 +
742 +config SYS_BOARD
743 + string "Board name"
744 + default "mt7621" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB
745 +
746 +config SYS_VENDOR
747 + default "mediatek" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB
748 +
749 +endif
750 --- /dev/null
751 +++ b/arch/mips/mach-mtmips/mt7621/Makefile
752 @@ -0,0 +1,14 @@
753 +# SPDX-License-Identifier: GPL-2.0
754 +
755 +obj-y += init.o
756 +obj-y += serial.o
757 +
758 +ifeq ($(CONFIG_SPL_BUILD),y)
759 +ifeq ($(CONFIG_TPL_BUILD),y)
760 +obj-y += tpl/
761 +else
762 +obj-y += spl/
763 +endif
764 +
765 +obj-y += sram_init.o
766 +endif
767 --- /dev/null
768 +++ b/arch/mips/mach-mtmips/mt7621/init.c
769 @@ -0,0 +1,246 @@
770 +// SPDX-License-Identifier: GPL-2.0
771 +/*
772 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
773 + *
774 + * Author: Weijie Gao <weijie.gao@mediatek.com>
775 + */
776 +
777 +#include <clk.h>
778 +#include <dm.h>
779 +#include <dm/uclass.h>
780 +#include <dt-bindings/clock/mt7621-clk.h>
781 +#include <asm/global_data.h>
782 +#include <linux/io.h>
783 +#include <linux/bitfield.h>
784 +#include "mt7621.h"
785 +
786 +DECLARE_GLOBAL_DATA_PTR;
787 +
788 +static const char *const boot_mode[(CHIP_MODE_M >> CHIP_MODE_S) + 1] = {
789 + [1] = "NAND 2K+64",
790 + [2] = "SPI-NOR 3-Byte Addr",
791 + [3] = "SPI-NOR 4-Byte Addr",
792 + [10] = "NAND 2K+128",
793 + [11] = "NAND 4K+128",
794 + [12] = "NAND 4K+256",
795 +};
796 +
797 +int print_cpuinfo(void)
798 +{
799 + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
800 + u32 val, ver, eco, pkg, core, dram, chipmode;
801 + u32 cpu_clk, ddr_clk, bus_clk, xtal_clk;
802 + struct udevice *clkdev;
803 + const char *bootdev;
804 + struct clk clk;
805 + int ret;
806 +
807 + val = readl(sysc + SYSCTL_CHIP_REV_ID_REG);
808 + ver = FIELD_GET(VER_ID_M, val);
809 + eco = FIELD_GET(ECO_ID_M, val);
810 + pkg = FIELD_GET(PKG_ID, val);
811 + core = FIELD_GET(CPU_ID, val);
812 +
813 + val = readl(sysc + SYSCTL_SYSCFG0_REG);
814 + dram = FIELD_GET(DRAM_TYPE, val);
815 + chipmode = FIELD_GET(CHIP_MODE_M, val);
816 +
817 + bootdev = boot_mode[chipmode];
818 + if (!bootdev)
819 + bootdev = "Unsupported boot mode";
820 +
821 + printf("CPU: MediaTek MT7621%c ver %u, eco %u\n",
822 + core ? (pkg ? 'A' : 'N') : 'S', ver, eco);
823 +
824 + printf("Boot: DDR%u, %s\n", dram ? 2 : 3, bootdev);
825 +
826 + ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7621_clk),
827 + &clkdev);
828 + if (ret)
829 + return ret;
830 +
831 + clk.dev = clkdev;
832 +
833 + clk.id = MT7621_CLK_CPU;
834 + cpu_clk = clk_get_rate(&clk);
835 +
836 + clk.id = MT7621_CLK_BUS;
837 + bus_clk = clk_get_rate(&clk);
838 +
839 + clk.id = MT7621_CLK_DDR;
840 + ddr_clk = clk_get_rate(&clk);
841 +
842 + clk.id = MT7621_CLK_XTAL;
843 + xtal_clk = clk_get_rate(&clk);
844 +
845 + /* Set final timer frequency */
846 + if (cpu_clk)
847 + gd->arch.timer_freq = cpu_clk / 2;
848 +
849 + printf("Clock: CPU: %uMHz, DDR: %uMT/s, Bus: %uMHz, XTAL: %uMHz\n",
850 + cpu_clk / 1000000, ddr_clk / 500000, bus_clk / 1000000,
851 + xtal_clk / 1000000);
852 +
853 + return 0;
854 +}
855 +
856 +unsigned long get_xtal_mhz(void)
857 +{
858 + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
859 + u32 bs, xtal_sel;
860 +
861 + bs = readl(sysc + SYSCTL_SYSCFG0_REG);
862 + xtal_sel = FIELD_GET(XTAL_MODE_SEL_M, bs);
863 +
864 + if (xtal_sel <= 2)
865 + return 20;
866 + else if (xtal_sel <= 5)
867 + return 40;
868 + else
869 + return 25;
870 +}
871 +
872 +static void xhci_config_40mhz(void __iomem *usbh)
873 +{
874 + writel(FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M, 0x20) |
875 + FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M, 0x20) |
876 + FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MODE_M, 2) |
877 + FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MODE_M, 2) | 0x10,
878 + usbh + SSUSB_MAC_CK_CTRL_REG);
879 +
880 + writel(FIELD_PREP(SSUSB_PLL_PREDIV_PE1D_M, 2) |
881 + FIELD_PREP(SSUSB_PLL_PREDIV_U3_M, 1) |
882 + FIELD_PREP(SSUSB_PLL_FBKDI_M, 4),
883 + usbh + DA_SSUSB_U3PHYA_10_REG);
884 +
885 + writel(FIELD_PREP(SSUSB_PLL_FBKDIV_PE2H_M, 0x18) |
886 + FIELD_PREP(SSUSB_PLL_FBKDIV_PE1D_M, 0x18) |
887 + FIELD_PREP(SSUSB_PLL_FBKDIV_PE1H_M, 0x18) |
888 + FIELD_PREP(SSUSB_PLL_FBKDIV_U3_M, 0x1e),
889 + usbh + DA_SSUSB_PLL_FBKDIV_REG);
890 +
891 + writel(FIELD_PREP(SSUSB_PLL_PCW_NCPO_U3_M, 0x1e400000),
892 + usbh + DA_SSUSB_PLL_PCW_NCPO_REG);
893 +
894 + writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE1H_M, 0x25) |
895 + FIELD_PREP(SSUSB_PLL_SSC_DELTA1_U3_M, 0x73),
896 + usbh + DA_SSUSB_PLL_SSC_DELTA1_REG);
897 +
898 + writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA_U3_M, 0x71) |
899 + FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE2D_M, 0x4a),
900 + usbh + DA_SSUSB_U3PHYA_21_REG);
901 +
902 + writel(FIELD_PREP(SSUSB_PLL_SSC_PRD_M, 0x140),
903 + usbh + SSUSB_U3PHYA_9_REG);
904 +
905 + writel(FIELD_PREP(SSUSB_SYSPLL_PCW_NCPO_M, 0x11c00000),
906 + usbh + SSUSB_U3PHYA_3_REG);
907 +
908 + writel(FIELD_PREP(SSUSB_PCIE_CLKDRV_AMP_M, 4) |
909 + FIELD_PREP(SSUSB_SYSPLL_FBSEL_M, 1) |
910 + FIELD_PREP(SSUSB_SYSPLL_PREDIV_M, 1),
911 + usbh + SSUSB_U3PHYA_1_REG);
912 +
913 + writel(FIELD_PREP(SSUSB_SYSPLL_FBDIV_M, 0x12) |
914 + SSUSB_SYSPLL_VCO_DIV_SEL | SSUSB_SYSPLL_FPEN |
915 + SSUSB_SYSPLL_MONCK_EN | SSUSB_SYSPLL_VOD_EN,
916 + usbh + SSUSB_U3PHYA_2_REG);
917 +
918 + writel(SSUSB_EQ_CURSEL | FIELD_PREP(SSUSB_RX_DAC_MUX_M, 8) |
919 + FIELD_PREP(SSUSB_PCIE_SIGDET_VTH_M, 1) |
920 + FIELD_PREP(SSUSB_PCIE_SIGDET_LPF_M, 1),
921 + usbh + SSUSB_U3PHYA_11_REG);
922 +
923 + writel(FIELD_PREP(SSUSB_RING_OSC_CNTEND_M, 0x1ff) |
924 + FIELD_PREP(SSUSB_XTAL_OSC_CNTEND_M, 0x7f) |
925 + SSUSB_RING_BYPASS_DET,
926 + usbh + SSUSB_B2_ROSC_0_REG);
927 +
928 + writel(FIELD_PREP(SSUSB_RING_OSC_FRC_RECAL_M, 3) |
929 + SSUSB_RING_OSC_FRC_SEL,
930 + usbh + SSUSB_B2_ROSC_1_REG);
931 +}
932 +
933 +static void xhci_config_25mhz(void __iomem *usbh)
934 +{
935 + writel(FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M, 0x20) |
936 + FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M, 0x20) |
937 + FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MODE_M, 2) |
938 + FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MODE_M, 2) | 0x10,
939 + usbh + SSUSB_MAC_CK_CTRL_REG);
940 +
941 + writel(FIELD_PREP(SSUSB_PLL_PREDIV_PE1D_M, 2) |
942 + FIELD_PREP(SSUSB_PLL_FBKDI_M, 4),
943 + usbh + DA_SSUSB_U3PHYA_10_REG);
944 +
945 + writel(FIELD_PREP(SSUSB_PLL_FBKDIV_PE2H_M, 0x18) |
946 + FIELD_PREP(SSUSB_PLL_FBKDIV_PE1D_M, 0x18) |
947 + FIELD_PREP(SSUSB_PLL_FBKDIV_PE1H_M, 0x18) |
948 + FIELD_PREP(SSUSB_PLL_FBKDIV_U3_M, 0x19),
949 + usbh + DA_SSUSB_PLL_FBKDIV_REG);
950 +
951 + writel(FIELD_PREP(SSUSB_PLL_PCW_NCPO_U3_M, 0x18000000),
952 + usbh + DA_SSUSB_PLL_PCW_NCPO_REG);
953 +
954 + writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE1H_M, 0x25) |
955 + FIELD_PREP(SSUSB_PLL_SSC_DELTA1_U3_M, 0x4a),
956 + usbh + DA_SSUSB_PLL_SSC_DELTA1_REG);
957 +
958 + writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA_U3_M, 0x48) |
959 + FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE2D_M, 0x4a),
960 + usbh + DA_SSUSB_U3PHYA_21_REG);
961 +
962 + writel(FIELD_PREP(SSUSB_PLL_SSC_PRD_M, 0x190),
963 + usbh + SSUSB_U3PHYA_9_REG);
964 +
965 + writel(FIELD_PREP(SSUSB_SYSPLL_PCW_NCPO_M, 0xe000000),
966 + usbh + SSUSB_U3PHYA_3_REG);
967 +
968 + writel(FIELD_PREP(SSUSB_PCIE_CLKDRV_AMP_M, 4) |
969 + FIELD_PREP(SSUSB_SYSPLL_FBSEL_M, 1),
970 + usbh + SSUSB_U3PHYA_1_REG);
971 +
972 + writel(FIELD_PREP(SSUSB_SYSPLL_FBDIV_M, 0xf) |
973 + SSUSB_SYSPLL_VCO_DIV_SEL | SSUSB_SYSPLL_FPEN |
974 + SSUSB_SYSPLL_MONCK_EN | SSUSB_SYSPLL_VOD_EN,
975 + usbh + SSUSB_U3PHYA_2_REG);
976 +
977 + writel(SSUSB_EQ_CURSEL | FIELD_PREP(SSUSB_RX_DAC_MUX_M, 8) |
978 + FIELD_PREP(SSUSB_PCIE_SIGDET_VTH_M, 1) |
979 + FIELD_PREP(SSUSB_PCIE_SIGDET_LPF_M, 1),
980 + usbh + SSUSB_U3PHYA_11_REG);
981 +
982 + writel(FIELD_PREP(SSUSB_RING_OSC_CNTEND_M, 0x1ff) |
983 + FIELD_PREP(SSUSB_XTAL_OSC_CNTEND_M, 0x7f) |
984 + SSUSB_RING_BYPASS_DET,
985 + usbh + SSUSB_B2_ROSC_0_REG);
986 +
987 + writel(FIELD_PREP(SSUSB_RING_OSC_FRC_RECAL_M, 3) |
988 + SSUSB_RING_OSC_FRC_SEL,
989 + usbh + SSUSB_B2_ROSC_1_REG);
990 +}
991 +
992 +void lowlevel_init(void)
993 +{
994 + void __iomem *usbh = ioremap_nocache(SSUSB_BASE, SSUSB_SIZE);
995 + u32 xtal = get_xtal_mhz();
996 +
997 + /* Setup USB xHCI */
998 + if (xtal == 40)
999 + xhci_config_40mhz(usbh);
1000 + else if (xtal == 25)
1001 + xhci_config_25mhz(usbh);
1002 +}
1003 +
1004 +ulong notrace get_tbclk(void)
1005 +{
1006 + return gd->arch.timer_freq;
1007 +}
1008 +
1009 +void _machine_restart(void)
1010 +{
1011 + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
1012 +
1013 + while (1)
1014 + writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG);
1015 +}
1016 --- /dev/null
1017 +++ b/arch/mips/mach-mtmips/mt7621/mt7621.h
1018 @@ -0,0 +1,229 @@
1019 +/* SPDX-License-Identifier: GPL-2.0 */
1020 +/*
1021 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1022 + *
1023 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1024 + */
1025 +
1026 +#ifndef _MT7621_H_
1027 +#define _MT7621_H_
1028 +
1029 +#define SYSCTL_BASE 0x1e000000
1030 +#define SYSCTL_SIZE 0x100
1031 +#define TIMER_BASE 0x1e000100
1032 +#define TIMER_SIZE 0x100
1033 +#define RBUS_BASE 0x1e000400
1034 +#define RBUS_SIZE 0x100
1035 +#define GPIO_BASE 0x1e000600
1036 +#define GPIO_SIZE 0x100
1037 +#define DMA_CFG_ARB_BASE 0x1e000800
1038 +#define DMA_CFG_ARB_SIZE 0x100
1039 +#define SPI_BASE 0x1e000b00
1040 +#define SPI_SIZE 0x100
1041 +#define UART1_BASE 0x1e000c00
1042 +#define UART1_SIZE 0x100
1043 +#define UART2_BASE 0x1e000d00
1044 +#define UART2_SIZE 0x100
1045 +#define UART3_BASE 0x1e000e00
1046 +#define UART3_SIZE 0x100
1047 +#define NFI_BASE 0x1e003000
1048 +#define NFI_SIZE 0x800
1049 +#define NFI_ECC_BASE 0x1e003800
1050 +#define NFI_ECC_SIZE 0x800
1051 +#define DRAMC_BASE 0x1e005000
1052 +#define DRAMC_SIZE 0x1000
1053 +#define FE_BASE 0x1e100000
1054 +#define FE_SIZE 0xe000
1055 +#define GMAC_BASE 0x1e110000
1056 +#define GMAC_SIZE 0x8000
1057 +#define SSUSB_BASE 0x1e1c0000
1058 +#define SSUSB_SIZE 0x40000
1059 +
1060 + /* GIC Base Address */
1061 +#define MIPS_GIC_BASE 0x1fbc0000
1062 +
1063 + /* CPC Base Address */
1064 +#define MIPS_CPC_BASE 0x1fbf0000
1065 +
1066 + /* Flash Memory-mapped Base Address */
1067 +#define FLASH_MMAP_BASE 0x1fc00000
1068 +#define TPL_INFO_OFFSET 0x40
1069 +#define TPL_INFO_MAGIC 0x31323637 /* Magic "7621" */
1070 +
1071 +/* SRAM */
1072 +#define FE_SRAM_BASE1 0x8000
1073 +#define FE_SRAM_BASE2 0xa000
1074 +
1075 +/* SYSCTL_BASE */
1076 +#define SYSCTL_CHIP_REV_ID_REG 0x0c
1077 +#define CPU_ID 0x20000
1078 +#define PKG_ID 0x10000
1079 +#define VER_ID_S 8
1080 +#define VER_ID_M 0xf00
1081 +#define ECO_ID_S 0
1082 +#define ECO_ID_M 0x0f
1083 +
1084 +#define SYSCTL_SYSCFG0_REG 0x10
1085 +#define XTAL_MODE_SEL_S 6
1086 +#define XTAL_MODE_SEL_M 0x1c0
1087 +#define DRAM_TYPE 0x10
1088 +#define CHIP_MODE_S 0
1089 +#define CHIP_MODE_M 0x0f
1090 +
1091 +#define BOOT_SRAM_BASE_REG 0x20
1092 +
1093 +#define SYSCTL_CLKCFG0_REG 0x2c
1094 +#define CPU_CLK_SEL_S 30
1095 +#define CPU_CLK_SEL_M 0xc0000000
1096 +#define MPLL_CFG_SEL_S 23
1097 +#define MPLL_CFG_SEL_M 0x800000
1098 +
1099 +#define SYSCTL_RSTCTL_REG 0x34
1100 +#define MCM_RST 0x04
1101 +#define SYS_RST 0x01
1102 +
1103 +#define SYSCTL_CUR_CLK_STS_REG 0x44
1104 +#define CUR_CPU_FDIV_S 8
1105 +#define CUR_CPU_FDIV_M 0x1f00
1106 +#define CUR_CPU_FFRAC_S 0
1107 +#define CUR_CPU_FFRAC_M 0x1f
1108 +
1109 +#define SYSCTL_GPIOMODE_REG 0x60
1110 +#define UART2_MODE_S 5
1111 +#define UART2_MODE_M 0x60
1112 +#define UART3_MODE_S 3
1113 +#define UART3_MODE_M 0x18
1114 +#define UART1_MODE 0x02
1115 +
1116 +/* RBUS_BASE */
1117 +#define RBUS_DYN_CFG0_REG 0x0010
1118 +#define CPU_FDIV_S 8
1119 +#define CPU_FDIV_M 0x1f00
1120 +#define CPU_FFRAC_S 0
1121 +#define CPU_FFRAC_M 0x1f
1122 +
1123 +/* DMA_CFG_ARB_BASE */
1124 +#define DMA_ROUTE_REG 0x000c
1125 +
1126 +/* SPI_BASE */
1127 +#define SPI_SPACE_REG 0x003c
1128 +#define FS_SLAVE_SEL_S 12
1129 +#define FS_SLAVE_SEL_M 0x70000
1130 +#define FS_CLK_SEL_S 0
1131 +#define FS_CLK_SEL_M 0xfff
1132 +
1133 +/* FE_BASE */
1134 +#define FE_RST_GLO_REG 0x0004
1135 +#define FE_PSE_RAM 0x04
1136 +#define FE_PSE_MEM_EN 0x02
1137 +#define FE_PSE_RESET 0x01
1138 +
1139 +/* SSUSB_BASE */
1140 +#define SSUSB_MAC_CK_CTRL_REG 0x10784
1141 +#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_S 16
1142 +#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M 0xff0000
1143 +#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_S 8
1144 +#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M 0xff00
1145 +#define SSUSB_MAC3_SYS_CK_GATE_MODE_S 2
1146 +#define SSUSB_MAC3_SYS_CK_GATE_MODE_M 0x0c
1147 +#define SSUSB_MAC2_SYS_CK_GATE_MODE_S 0
1148 +#define SSUSB_MAC2_SYS_CK_GATE_MODE_M 0x03
1149 +
1150 +#define SSUSB_B2_ROSC_0_REG 0x10a40
1151 +#define SSUSB_RING_OSC_CNTEND_S 23
1152 +#define SSUSB_RING_OSC_CNTEND_M 0xff800000
1153 +#define SSUSB_XTAL_OSC_CNTEND_S 16
1154 +#define SSUSB_XTAL_OSC_CNTEND_M 0x7f0000
1155 +#define SSUSB_RING_BYPASS_DET 0x01
1156 +
1157 +#define SSUSB_B2_ROSC_1_REG 0x10a44
1158 +#define SSUSB_RING_OSC_FRC_RECAL_S 17
1159 +#define SSUSB_RING_OSC_FRC_RECAL_M 0x60000
1160 +#define SSUSB_RING_OSC_FRC_SEL 0x01
1161 +
1162 +#define SSUSB_U3PHYA_1_REG 0x10b04
1163 +#define SSUSB_PCIE_CLKDRV_AMP_S 27
1164 +#define SSUSB_PCIE_CLKDRV_AMP_M 0x38000000
1165 +#define SSUSB_SYSPLL_FBSEL_S 2
1166 +#define SSUSB_SYSPLL_FBSEL_M 0x0c
1167 +#define SSUSB_SYSPLL_PREDIV_S 0
1168 +#define SSUSB_SYSPLL_PREDIV_M 0x03
1169 +
1170 +#define SSUSB_U3PHYA_2_REG 0x10b08
1171 +#define SSUSB_SYSPLL_FBDIV_S 24
1172 +#define SSUSB_SYSPLL_FBDIV_M 0x7f000000
1173 +#define SSUSB_SYSPLL_VCO_DIV_SEL 0x200000
1174 +#define SSUSB_SYSPLL_FPEN 0x2000
1175 +#define SSUSB_SYSPLL_MONCK_EN 0x1000
1176 +#define SSUSB_SYSPLL_VOD_EN 0x200
1177 +
1178 +#define SSUSB_U3PHYA_3_REG 0x10b10
1179 +#define SSUSB_SYSPLL_PCW_NCPO_S 1
1180 +#define SSUSB_SYSPLL_PCW_NCPO_M 0xfffffffe
1181 +
1182 +#define SSUSB_U3PHYA_9_REG 0x10b24
1183 +#define SSUSB_PLL_SSC_PRD_S 0
1184 +#define SSUSB_PLL_SSC_PRD_M 0xffff
1185 +
1186 +#define SSUSB_U3PHYA_11_REG 0x10b2c
1187 +#define SSUSB_EQ_CURSEL 0x1000000
1188 +#define SSUSB_RX_DAC_MUX_S 19
1189 +#define SSUSB_RX_DAC_MUX_M 0xf80000
1190 +#define SSUSB_PCIE_SIGDET_VTH_S 5
1191 +#define SSUSB_PCIE_SIGDET_VTH_M 0x60
1192 +#define SSUSB_PCIE_SIGDET_LPF_S 3
1193 +#define SSUSB_PCIE_SIGDET_LPF_M 0x18
1194 +
1195 +#define DA_SSUSB_PLL_FBKDIV_REG 0x10c1c
1196 +#define SSUSB_PLL_FBKDIV_PE2H_S 24
1197 +#define SSUSB_PLL_FBKDIV_PE2H_M 0x7f000000
1198 +#define SSUSB_PLL_FBKDIV_PE1D_S 16
1199 +#define SSUSB_PLL_FBKDIV_PE1D_M 0x7f0000
1200 +#define SSUSB_PLL_FBKDIV_PE1H_S 8
1201 +#define SSUSB_PLL_FBKDIV_PE1H_M 0x7f00
1202 +#define SSUSB_PLL_FBKDIV_U3_S 0
1203 +#define SSUSB_PLL_FBKDIV_U3_M 0x7f
1204 +
1205 +#define DA_SSUSB_U3PHYA_10_REG 0x10c20
1206 +#define SSUSB_PLL_PREDIV_PE1D_S 18
1207 +#define SSUSB_PLL_PREDIV_PE1D_M 0xc0000
1208 +#define SSUSB_PLL_PREDIV_U3_S 8
1209 +#define SSUSB_PLL_PREDIV_U3_M 0x300
1210 +#define SSUSB_PLL_FBKDI_S 0
1211 +#define SSUSB_PLL_FBKDI_M 0x07
1212 +
1213 +#define DA_SSUSB_PLL_PCW_NCPO_REG 0x10c24
1214 +#define SSUSB_PLL_PCW_NCPO_U3_S 0
1215 +#define SSUSB_PLL_PCW_NCPO_U3_M 0x7fffffff
1216 +
1217 +#define DA_SSUSB_PLL_SSC_DELTA1_REG 0x10c38
1218 +#define SSUSB_PLL_SSC_DELTA1_PE1H_S 16
1219 +#define SSUSB_PLL_SSC_DELTA1_PE1H_M 0xffff0000
1220 +#define SSUSB_PLL_SSC_DELTA1_U3_S 0
1221 +#define SSUSB_PLL_SSC_DELTA1_U3_M 0xffff
1222 +
1223 +#define DA_SSUSB_U3PHYA_21_REG 0x10c40
1224 +#define SSUSB_PLL_SSC_DELTA_U3_S 16
1225 +#define SSUSB_PLL_SSC_DELTA_U3_M 0xffff0000
1226 +#define SSUSB_PLL_SSC_DELTA1_PE2D_S 0
1227 +#define SSUSB_PLL_SSC_DELTA1_PE2D_M 0xffff
1228 +
1229 +/* MT7621 specific CM values */
1230 +
1231 +/* GCR_REGx_BASE */
1232 +#define GCR_REG0_BASE_VALUE 0x1c000000
1233 +#define GCR_REG1_BASE_VALUE 0x60000000
1234 +#define GCR_REG2_BASE_VALUE 0x1c000000
1235 +#define GCR_REG3_BASE_VALUE 0x1c000000
1236 +
1237 +/* GCR_REGx_MASK */
1238 +#define GCR_REG0_MASK_VALUE 0x0000fc00 /* 64M Bus */
1239 +#define GCR_REG1_MASK_VALUE 0x0000f000 /* 256M PCI Mem */
1240 +#define GCR_REG2_MASK_VALUE 0x0000fc00 /* unused */
1241 +#define GCR_REG3_MASK_VALUE 0x0000fc00 /* unused */
1242 +
1243 +#ifndef __ASSEMBLY__
1244 +unsigned long get_xtal_mhz(void);
1245 +#endif
1246 +
1247 +#endif /* _MT7621_H_ */
1248 --- /dev/null
1249 +++ b/arch/mips/mach-mtmips/mt7621/serial.c
1250 @@ -0,0 +1,23 @@
1251 +// SPDX-License-Identifier: GPL-2.0
1252 +/*
1253 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1254 + *
1255 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1256 + */
1257 +
1258 +#include <asm/io.h>
1259 +#include <asm/addrspace.h>
1260 +#include "mt7621.h"
1261 +
1262 +void board_debug_uart_init(void)
1263 +{
1264 + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
1265 +
1266 +#if CONFIG_DEBUG_UART_BASE == 0xbe000c00 /* KSEG1ADDR(UART1_BASE) */
1267 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE);
1268 +#elif CONFIG_DEBUG_UART_BASE == 0xbe000d00 /* KSEG1ADDR(UART2_BASE) */
1269 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M);
1270 +#elif CONFIG_DEBUG_UART_BASE == 0xbe000e00 /* KSEG1ADDR(UART3_BASE) */
1271 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M);
1272 +#endif
1273 +}
1274 --- /dev/null
1275 +++ b/arch/mips/mach-mtmips/mt7621/spl/Makefile
1276 @@ -0,0 +1,9 @@
1277 +
1278 +extra-y += start.o
1279 +
1280 +obj-y += spl.o
1281 +obj-y += cps.o
1282 +obj-y += dram.o
1283 +obj-y += serial.o
1284 +obj-y += launch.o
1285 +obj-y += launch_ll.o
1286 --- /dev/null
1287 +++ b/arch/mips/mach-mtmips/mt7621/spl/cps.c
1288 @@ -0,0 +1,153 @@
1289 +// SPDX-License-Identifier: GPL-2.0
1290 +/*
1291 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1292 + *
1293 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1294 + */
1295 +
1296 +#include <asm/io.h>
1297 +#include <asm/addrspace.h>
1298 +#include <asm/mipsregs.h>
1299 +#include <asm/cm.h>
1300 +#include <linux/bitfield.h>
1301 +#include "../mt7621.h"
1302 +
1303 +/* GIC Shared Register Bases */
1304 +#define GIC_SH_POL_BASE 0x100
1305 +#define GIC_SH_TRIG_BASE 0x180
1306 +#define GIC_SH_RMASK_BASE 0x300
1307 +#define GIC_SH_SMASK_BASE 0x380
1308 +#define GIC_SH_MASK_BASE 0x400
1309 +#define GIC_SH_PEND_BASE 0x480
1310 +#define GIC_SH_MAP_PIN_BASE 0x500
1311 +#define GIC_SH_MAP_VPE_BASE 0x2000
1312 +
1313 +/* GIC Registers */
1314 +#define GIC_SH_POL31_0 (GIC_SH_POL_BASE + 0x00)
1315 +#define GIC_SH_POL63_32 (GIC_SH_POL_BASE + 0x04)
1316 +
1317 +#define GIC_SH_TRIG31_0 (GIC_SH_TRIG_BASE + 0x00)
1318 +#define GIC_SH_TRIG63_32 (GIC_SH_TRIG_BASE + 0x04)
1319 +
1320 +#define GIC_SH_RMASK31_0 (GIC_SH_RMASK_BASE + 0x00)
1321 +#define GIC_SH_RMASK63_32 (GIC_SH_RMASK_BASE + 0x04)
1322 +
1323 +#define GIC_SH_SMASK31_0 (GIC_SH_SMASK_BASE + 0x00)
1324 +#define GIC_SH_SMASK63_32 (GIC_SH_SMASK_BASE + 0x04)
1325 +
1326 +#define GIC_SH_MAP_PIN(n) (GIC_SH_MAP_PIN_BASE + (n) * 4)
1327 +
1328 +#define GIC_SH_MAP_VPE(n, v) (GIC_SH_MAP_VPE_BASE + (n) * 0x20 + ((v) / 32) * 4)
1329 +#define GIC_SH_MAP_VPE31_0(n) GIC_SH_MAP_VPE(n, 0)
1330 +
1331 +/* GIC_SH_MAP_PIN fields */
1332 +#define GIC_MAP_TO_PIN BIT(31)
1333 +#define GIC_MAP_TO_NMI BIT(30)
1334 +#define GIC_MAP GENMASK(5, 0)
1335 +#define GIC_MAP_SHIFT 0
1336 +
1337 +static void cm_init(void __iomem *cm_base)
1338 +{
1339 + u32 gcrcfg, num_cores;
1340 +
1341 + gcrcfg = readl(cm_base + GCR_CONFIG);
1342 + num_cores = FIELD_GET(GCR_CONFIG_PCORES, gcrcfg) + 1;
1343 +
1344 + writel((1 << num_cores) - 1, cm_base + GCR_ACCESS);
1345 +
1346 + writel(GCR_REG0_BASE_VALUE, cm_base + GCR_REG0_BASE);
1347 + writel(GCR_REG1_BASE_VALUE, cm_base + GCR_REG1_BASE);
1348 + writel(GCR_REG2_BASE_VALUE, cm_base + GCR_REG2_BASE);
1349 + writel(GCR_REG3_BASE_VALUE, cm_base + GCR_REG3_BASE);
1350 +
1351 + clrsetbits_32(cm_base + GCR_REG0_MASK,
1352 + GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT,
1353 + FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG0_MASK_VALUE) |
1354 + GCR_REGn_MASK_CMTGT_IOCU0);
1355 +
1356 + clrsetbits_32(cm_base + GCR_REG1_MASK,
1357 + GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT,
1358 + FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG1_MASK_VALUE) |
1359 + GCR_REGn_MASK_CMTGT_IOCU0);
1360 +
1361 + clrsetbits_32(cm_base + GCR_REG2_MASK,
1362 + GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT,
1363 + FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG2_MASK_VALUE) |
1364 + GCR_REGn_MASK_CMTGT_IOCU0);
1365 +
1366 + clrsetbits_32(cm_base + GCR_REG3_MASK,
1367 + GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT,
1368 + FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG3_MASK_VALUE) |
1369 + GCR_REGn_MASK_CMTGT_IOCU0);
1370 +
1371 + clrbits_32(cm_base + GCR_BASE, CM_DEFAULT_TARGET_MASK);
1372 + setbits_32(cm_base + GCR_CONTROL, GCR_CONTROL_SYNCCTL);
1373 +}
1374 +
1375 +static void gic_init(void)
1376 +{
1377 + void __iomem *gic_base = (void *)KSEG1ADDR(MIPS_GIC_BASE);
1378 + int i;
1379 +
1380 + /* Interrupt 0..5: Level Trigger, Active High */
1381 + writel(0, gic_base + GIC_SH_TRIG31_0);
1382 + writel(0x3f, gic_base + GIC_SH_RMASK31_0);
1383 + writel(0x3f, gic_base + GIC_SH_POL31_0);
1384 + writel(0x3f, gic_base + GIC_SH_SMASK31_0);
1385 +
1386 + /* Interrupt 56..63: Edge Trigger, Rising Edge */
1387 + /* Hardcoded to set up the last 8 external interrupts for IPI. */
1388 + writel(0xff000000, gic_base + GIC_SH_TRIG63_32);
1389 + writel(0xff000000, gic_base + GIC_SH_RMASK63_32);
1390 + writel(0xff000000, gic_base + GIC_SH_POL63_32);
1391 + writel(0xff000000, gic_base + GIC_SH_SMASK63_32);
1392 +
1393 + /* Map interrupt source to particular hardware interrupt pin */
1394 + /* source {0,1,2,3,4,5} -> pin {0,0,4,3,0,5} */
1395 + writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(0));
1396 + writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(1));
1397 + writel(GIC_MAP_TO_PIN | 4, gic_base + GIC_SH_MAP_PIN(2));
1398 + writel(GIC_MAP_TO_PIN | 3, gic_base + GIC_SH_MAP_PIN(3));
1399 + writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(4));
1400 + writel(GIC_MAP_TO_PIN | 5, gic_base + GIC_SH_MAP_PIN(5));
1401 +
1402 + /* source 56~59 -> pin 1, 60~63 -> pin 2 */
1403 + writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(56));
1404 + writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(57));
1405 + writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(58));
1406 + writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(59));
1407 + writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(60));
1408 + writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(61));
1409 + writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(62));
1410 + writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(63));
1411 +
1412 + /* Interrupt map to VPE (bit mask) */
1413 + for (i = 0; i < 32; i++)
1414 + writel(BIT(0), gic_base + GIC_SH_MAP_VPE31_0(i));
1415 +
1416 + /*
1417 + * Direct GIC_int 56..63 to vpe 0..3
1418 + * MIPS Linux convention that last 16 interrupts implemented be set
1419 + * aside for IPI signaling.
1420 + * The actual interrupts are tied low and software sends interrupts
1421 + * via GIC_SH_WEDGE writes.
1422 + */
1423 + for (i = 0; i < 4; i++) {
1424 + writel(BIT(i), gic_base + GIC_SH_MAP_VPE31_0(i + 56));
1425 + writel(BIT(i), gic_base + GIC_SH_MAP_VPE31_0(i + 60));
1426 + }
1427 +}
1428 +
1429 +void mt7621_cps_init(void)
1430 +{
1431 + void __iomem *cm_base = (void *)KSEG1ADDR(CONFIG_MIPS_CM_BASE);
1432 +
1433 + /* Enable GIC */
1434 + writel(MIPS_GIC_BASE | GCR_GIC_EN, cm_base + GCR_GIC_BASE);
1435 +
1436 + /* Enable CPC */
1437 + writel(MIPS_CPC_BASE | GCR_CPC_EN, cm_base + GCR_CPC_BASE);
1438 +
1439 + gic_init();
1440 + cm_init(cm_base);
1441 +}
1442 --- /dev/null
1443 +++ b/arch/mips/mach-mtmips/mt7621/spl/dram.c
1444 @@ -0,0 +1,153 @@
1445 +// SPDX-License-Identifier: GPL-2.0
1446 +/*
1447 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1448 + *
1449 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1450 + */
1451 +
1452 +#include <vsprintf.h>
1453 +#include <asm/io.h>
1454 +#include <asm/sections.h>
1455 +#include <asm/byteorder.h>
1456 +#include <asm/addrspace.h>
1457 +#include <linux/string.h>
1458 +#include "../mt7621.h"
1459 +#include "dram.h"
1460 +
1461 +static const u32 ddr2_act[DDR_PARAM_SIZE] = {
1462 +#if defined(CONFIG_MT7621_DRAM_DDR2_512M)
1463 + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174441,
1464 + 0x00000000, 0xF0748661, 0x40001273, 0x9F0A0481,
1465 + 0x0304692F, 0x15602842, 0x00008888, 0x88888888,
1466 + 0x00000000, 0x00000000, 0x00000000, 0x07100000,
1467 + 0x00001B63, 0x00002000, 0x00004000, 0x00006000,
1468 + 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1469 +#elif defined(CONFIG_MT7621_DRAM_DDR2_512M_W9751G6KB_A02_1066MHZ)
1470 + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x33484584,
1471 + 0x00000000, 0xF07486A1, 0x50001273, 0x9F010481,
1472 + 0x0304693F, 0x15602842, 0x00008888, 0x88888888,
1473 + 0x00000000, 0x00000000, 0x00000010, 0x07100000,
1474 + 0x00001F73, 0x00002000, 0x00004000, 0x00006000,
1475 + 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1476 +#elif defined(CONFIG_MT7621_DRAM_DDR2_1024M_W971GG6KB25_800MHZ)
1477 + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174430,
1478 + 0x01000000, 0xF0748661, 0x40001273, 0x9F0F0481,
1479 + 0x0304692F, 0x15602842, 0x00008888, 0x88888888,
1480 + 0x00000000, 0x00000000, 0x00000000, 0x07100000,
1481 + 0x00001B63, 0x00002000, 0x00004000, 0x00006000,
1482 + 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1483 +#elif defined(CONFIG_MT7621_DRAM_DDR2_1024M_W971GG6KB18_1066MHZ)
1484 + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x33484584,
1485 + 0x01000000, 0xF07486A1, 0x50001273, 0x9F070481,
1486 + 0x0304693F, 0x15602842, 0x00008888, 0x88888888,
1487 + 0x00000000, 0x00000000, 0x00000010, 0x07100000,
1488 + 0x00001F73, 0x00002000, 0x00004000, 0x00006000,
1489 + 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1490 +#else /* CONFIG_MT7621_DRAM_DDR2_1024M */
1491 + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174441,
1492 + 0x01000000, 0xF0748661, 0x40001273, 0x9F0F0481,
1493 + 0x0304692F, 0x15602842, 0x00008888, 0x88888888,
1494 + 0x00000000, 0x00000000, 0x00000000, 0x07100000,
1495 + 0x00001B63, 0x00002000, 0x00004000, 0x00006000,
1496 + 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1497 +#endif
1498 +};
1499 +
1500 +static const u32 ddr3_act[DDR_PARAM_SIZE] = {
1501 +#if defined(CONFIG_MT7621_DRAM_DDR3_1024M)
1502 + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694683,
1503 + 0x01000000, 0xF07486A1, 0xC287221D, 0x9F060481,
1504 + 0x03046948, 0x15602842, 0x00008888, 0x88888888,
1505 + 0x00000000, 0x00000000, 0x00000210, 0x07100000,
1506 + 0x00001B61, 0x00002040, 0x00004010, 0x00006000,
1507 + 0x0C000000, 0x07070000, 0x00000000, 0x00000000,
1508 +#elif defined(CONFIG_MT7621_DRAM_DDR3_4096M)
1509 + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694683,
1510 + 0x01000000, 0xF07486A1, 0xC287221D, 0x9F0F0481,
1511 + 0x03046948, 0x15602842, 0x00008888, 0x88888888,
1512 + 0x00000000, 0x00000000, 0x00000240, 0x07100000,
1513 + 0x00001B61, 0x00002040, 0x00004010, 0x00006000,
1514 + 0x0C000000, 0x07070000, 0x00000000, 0x00000000,
1515 +#elif defined(CONFIG_MT7621_DRAM_DDR3_1024M_KGD)
1516 + 0xFF00FF00, 0xFF00FF00, 0x00000007, 0x44694683,
1517 + 0x01000000, 0xF07406A1, 0xC287221D, 0x9F060481,
1518 + 0x03046923, 0x152f2842, 0x00008888, 0x88888888,
1519 + 0x00000000, 0x00000000, 0x00000210, 0x07100000,
1520 + 0x00001B61, 0x00002040, 0x00004010, 0x00006000,
1521 + 0x0C000000, 0x07070000, 0x000C0000, 0x00000000,
1522 +#else /* CONFIG_MT7621_DRAM_DDR3_2048M */
1523 + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694673,
1524 + 0x01000000, 0xF07486A1, 0xC287221D, 0x9F050481,
1525 + 0x03046948, 0x15602842, 0x00008888, 0x88888888,
1526 + 0x00000000, 0x00000000, 0x00000220, 0x07100000,
1527 + 0x00001B61, 0x00002040, 0x00004010, 0x00006000,
1528 + 0x0C000000, 0x07070000, 0x00000000, 0x00000000,
1529 +#endif
1530 +};
1531 +
1532 +#if defined(CONFIG_MT7621_DRAM_FREQ_400)
1533 +#define DDR_FREQ_PARAM 0x41000000
1534 +#elif defined(CONFIG_MT7621_DRAM_FREQ_1066)
1535 +#define DDR_FREQ_PARAM 0x21000000
1536 +#elif defined(CONFIG_MT7621_DRAM_FREQ_1200)
1537 +#define DDR_FREQ_PARAM 0x11000000
1538 +#else /* CONFIG_MT7621_DRAM_FREQ_800 */
1539 +#define DDR_FREQ_PARAM 0x31000000
1540 +#endif
1541 +
1542 +#define RG_MEPL_FBDIV_S 4
1543 +#define RG_MEPL_FBDIV_M 0x7f
1544 +
1545 +static inline void word_copy(u32 *dest, const u32 *src, u32 count)
1546 +{
1547 + u32 i;
1548 +
1549 + for (i = 0; i < count; i++)
1550 + dest[i] = src[i];
1551 +}
1552 +
1553 +static u32 calc_cpu_pll_val(void)
1554 +{
1555 + u32 div, baseval, fb;
1556 +
1557 + div = get_xtal_mhz();
1558 +
1559 + if (div == 40) {
1560 + div /= 2;
1561 + baseval = 0xc0005802;
1562 + } else {
1563 + baseval = 0xc0004802;
1564 + }
1565 +
1566 + fb = CONFIG_MT7621_CPU_FREQ / div - 1;
1567 + if (fb > RG_MEPL_FBDIV_M)
1568 + fb = RG_MEPL_FBDIV_M;
1569 +
1570 + return baseval | (fb << RG_MEPL_FBDIV_S);
1571 +}
1572 +
1573 +void prepare_stage_bin(void)
1574 +{
1575 + u32 stage_size;
1576 +
1577 + const struct stage_header *stock_stage_bin =
1578 + (const struct stage_header *)__image_copy_end;
1579 +
1580 + struct stage_header *new_stage_bin =
1581 + (struct stage_header *)STAGE_LOAD_ADDR;
1582 +
1583 + if (be32_to_cpu(stock_stage_bin->ep) != STAGE_LOAD_ADDR)
1584 + panic("Invalid DDR stage binary blob\n");
1585 +
1586 + stage_size = be32_to_cpu(stock_stage_bin->stage_size);
1587 +
1588 + word_copy((u32 *)new_stage_bin, (const u32 *)stock_stage_bin,
1589 + (stage_size + sizeof(u32) - 1) / sizeof(u32));
1590 +
1591 + word_copy(new_stage_bin->ddr2_act, ddr2_act, DDR_PARAM_SIZE);
1592 + word_copy(new_stage_bin->ddr3_act, ddr3_act, DDR_PARAM_SIZE);
1593 +
1594 + new_stage_bin->cpu_pll_cfg = calc_cpu_pll_val();
1595 + new_stage_bin->ddr_pll_cfg = DDR_FREQ_PARAM;
1596 + new_stage_bin->baudrate = CONFIG_BAUDRATE;
1597 +}
1598 --- /dev/null
1599 +++ b/arch/mips/mach-mtmips/mt7621/spl/dram.h
1600 @@ -0,0 +1,39 @@
1601 +/* SPDX-License-Identifier: GPL-2.0 */
1602 +/*
1603 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1604 + *
1605 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1606 + */
1607 +
1608 +#ifndef _MT7621_DRAM_H_
1609 +#define _MT7621_DRAM_H_
1610 +
1611 +#define STAGE_LOAD_ADDR 0xBE108800
1612 +
1613 +#ifndef __ASSEMBLY__
1614 +#include <linux/types.h>
1615 +
1616 +#define DDR_PARAM_SIZE 24
1617 +
1618 +struct stage_header {
1619 + u32 jump_insn[2];
1620 + u32 ep;
1621 + u32 stage_size;
1622 + u32 has_stage2;
1623 + u32 next_ep;
1624 + u32 next_size;
1625 + u32 next_offset;
1626 + u32 cpu_pll_cfg;
1627 + u32 ddr_pll_cfg;
1628 + u32 reserved2[6];
1629 + char build_tag[32];
1630 + u32 ddr3_act[DDR_PARAM_SIZE];
1631 + u32 padding1[2];
1632 + u32 ddr2_act[DDR_PARAM_SIZE];
1633 + u32 padding2[2];
1634 + u32 baudrate;
1635 + u32 padding3;
1636 +};
1637 +#endif
1638 +
1639 +#endif /* _MT7621_DRAM_H_ */
1640 --- /dev/null
1641 +++ b/arch/mips/mach-mtmips/mt7621/spl/launch.c
1642 @@ -0,0 +1,100 @@
1643 +// SPDX-License-Identifier: GPL-2.0
1644 +/*
1645 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1646 + *
1647 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1648 + */
1649 +
1650 +#include <asm/io.h>
1651 +#include <asm/cm.h>
1652 +#include <asm/sections.h>
1653 +#include <asm/addrspace.h>
1654 +#include <asm/mipsmtregs.h>
1655 +#include <linux/sizes.h>
1656 +#include <time.h>
1657 +#include <cpu_func.h>
1658 +#include "launch.h"
1659 +#include "../mt7621.h"
1660 +
1661 +/* Cluster Power Controller (CPC) offsets */
1662 +#define CPC_CL_OTHER 0x2010
1663 +#define CPC_CO_CMD 0x4000
1664 +
1665 +/* CPC_CL_OTHER fields */
1666 +#define CPC_CL_OTHER_CORENUM_SHIFT 16
1667 +#define CPC_CL_OTHER_CORENUM GENMASK(23, 16)
1668 +
1669 +/* CPC_CO_CMD */
1670 +#define PWR_UP 3
1671 +
1672 +#define NUM_CORES 2
1673 +#define NUM_CPUS 4
1674 +#define WAIT_CPUS_TIMEOUT 4000
1675 +
1676 +static void copy_launch_wait_code(void)
1677 +{
1678 + memset((void *)KSEG1, 0, SZ_4K);
1679 +
1680 + memcpy((void *)KSEG1ADDR(LAUNCH_WAITCODE),
1681 + &launch_wait_code_start,
1682 + &launch_wait_code_end - &launch_wait_code_start);
1683 +
1684 + invalidate_dcache_range(KSEG0, SZ_4K);
1685 +}
1686 +
1687 +static void bootup_secondary_core(void)
1688 +{
1689 + void __iomem *cpcbase = (void __iomem *)KSEG1ADDR(MIPS_CPC_BASE);
1690 + int i;
1691 +
1692 + for (i = 1; i < NUM_CORES; i++) {
1693 + writel(i << CPC_CL_OTHER_CORENUM_SHIFT, cpcbase + CPC_CL_OTHER);
1694 + writel(PWR_UP, cpcbase + CPC_CO_CMD);
1695 + }
1696 +}
1697 +
1698 +void secondary_cpu_init(void)
1699 +{
1700 + void __iomem *sysc = (void __iomem *)KSEG1ADDR(SYSCTL_BASE);
1701 + u32 i, dual_core = 0, cpuready = 1, cpumask = 0x03;
1702 + ulong wait_tick;
1703 + struct cpulaunch_t *c;
1704 +
1705 + /* Copy LAUNCH wait code used by other VPEs */
1706 + copy_launch_wait_code();
1707 +
1708 + dual_core = readl(sysc + SYSCTL_CHIP_REV_ID_REG) & CPU_ID;
1709 +
1710 + if (dual_core) {
1711 + /* Bootup secondary core for MT7621A */
1712 + cpumask = 0x0f;
1713 +
1714 + /* Make BootROM/TPL redirect Core1's bootup flow to our entry point */
1715 + writel((uintptr_t)&_start, sysc + BOOT_SRAM_BASE_REG);
1716 +
1717 + bootup_secondary_core();
1718 + }
1719 +
1720 + /* Join the coherent domain */
1721 + join_coherent_domain(dual_core ? 2 : 1);
1722 +
1723 + /* Bootup Core0/VPE1 */
1724 + boot_vpe1();
1725 +
1726 + /* Wait for all CPU ready */
1727 + wait_tick = get_timer(0) + WAIT_CPUS_TIMEOUT;
1728 +
1729 + while (time_before(get_timer(0), wait_tick)) {
1730 + /* CPU0 is obviously ready */
1731 + for (i = 1; i < NUM_CPUS; i++) {
1732 + c = (struct cpulaunch_t *)(KSEG0ADDR(CPULAUNCH) +
1733 + (i << LOG2CPULAUNCH));
1734 +
1735 + if (c->flags & LAUNCH_FREADY)
1736 + cpuready |= BIT(i);
1737 + }
1738 +
1739 + if ((cpuready & cpumask) == cpumask)
1740 + break;
1741 + }
1742 +}
1743 --- /dev/null
1744 +++ b/arch/mips/mach-mtmips/mt7621/spl/launch.h
1745 @@ -0,0 +1,52 @@
1746 +/* SPDX-License-Identifier: GPL-2.0 */
1747 +/*
1748 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1749 + *
1750 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1751 + */
1752 +
1753 +#ifndef _LAUNCH_H_
1754 +#define _LAUNCH_H_
1755 +
1756 +#ifndef __ASSEMBLY__
1757 +
1758 +struct cpulaunch_t {
1759 + unsigned long pc;
1760 + unsigned long gp;
1761 + unsigned long sp;
1762 + unsigned long a0;
1763 + unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */
1764 + unsigned long flags;
1765 +};
1766 +
1767 +extern char launch_wait_code_start;
1768 +extern char launch_wait_code_end;
1769 +
1770 +void join_coherent_domain(int ncores);
1771 +void boot_vpe1(void);
1772 +
1773 +#else
1774 +
1775 +#define LAUNCH_PC 0
1776 +#define LAUNCH_GP 4
1777 +#define LAUNCH_SP 8
1778 +#define LAUNCH_A0 12
1779 +#define LAUNCH_FLAGS 28
1780 +
1781 +#endif
1782 +
1783 +#define LOG2CPULAUNCH 5
1784 +
1785 +#define LAUNCH_FREADY 1
1786 +#define LAUNCH_FGO 2
1787 +#define LAUNCH_FGONE 4
1788 +
1789 +#define LAUNCH_WAITCODE 0x00000d00
1790 +#define SCRLAUNCH 0x00000e00
1791 +#define CPULAUNCH 0x00000f00
1792 +#define NCPULAUNCH 8
1793 +
1794 +/* Polling period in count cycles for secondary CPU's */
1795 +#define LAUNCHPERIOD 10000
1796 +
1797 +#endif /* _LAUNCH_H_ */
1798 --- /dev/null
1799 +++ b/arch/mips/mach-mtmips/mt7621/spl/launch_ll.S
1800 @@ -0,0 +1,339 @@
1801 +/* SPDX-License-Identifier: GPL-2.0 */
1802 +/*
1803 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1804 + *
1805 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1806 + */
1807 +
1808 +#include <asm/cm.h>
1809 +#include <asm/asm.h>
1810 +#include <asm/regdef.h>
1811 +#include <asm/cacheops.h>
1812 +#include <asm/mipsregs.h>
1813 +#include <asm/addrspace.h>
1814 +#include <asm/mipsmtregs.h>
1815 +#include "launch.h"
1816 +
1817 + .macro cache_loop curr, end, line_sz, op
1818 +10: cache \op, 0(\curr)
1819 + PTR_ADDU \curr, \curr, \line_sz
1820 + bne \curr, \end, 10b
1821 + .endm
1822 +
1823 + .set mt
1824 +
1825 +/*
1826 + * Join the coherent domain
1827 + * a0 = number of cores
1828 + */
1829 +LEAF(join_coherent_domain)
1830 + /*
1831 + * Enable coherence and allow interventions from all other cores.
1832 + * (Write access enabled via GCR_ACCESS by core 0.)
1833 + */
1834 + li t1, 1
1835 + sll t1, a0
1836 + addiu t1, -1
1837 +
1838 + li t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE)
1839 + sw t1, GCR_Cx_COHERENCE(t0)
1840 + ehb
1841 +
1842 + move t2, zero
1843 +
1844 +_next_coherent_core:
1845 + sll t1, t2, GCR_Cx_OTHER_CORENUM_SHIFT
1846 + sw t1, GCR_Cx_OTHER(t0)
1847 +
1848 +_busy_wait_coherent_core:
1849 + lw t1, GCR_CO_COHERENCE(t0)
1850 + beqz t1, _busy_wait_coherent_core
1851 +
1852 + addiu t2, 1
1853 + bne t2, a0, _next_coherent_core
1854 +
1855 + jr ra
1856 + END(join_coherent_domain)
1857 +
1858 +/*
1859 + * All VPEs other than VPE0 will go here.
1860 + */
1861 +LEAF(launch_vpe_entry)
1862 + mfc0 t0, CP0_EBASE
1863 + and t0, t0, MIPS_EBASE_CPUNUM
1864 +
1865 + /* per-VPE cpulaunch_t */
1866 + li a0, KSEG0ADDR(CPULAUNCH)
1867 + sll t1, t0, LOG2CPULAUNCH
1868 + addu a0, t1
1869 +
1870 + /* Set CPU online flag */
1871 + li t0, LAUNCH_FREADY
1872 + sw t0, LAUNCH_FLAGS(a0)
1873 +
1874 + /* Enable count interrupt in mask, but do not enable interrupts */
1875 + mfc0 t0, CP0_STATUS
1876 + ori t0, STATUSF_IP7
1877 + mtc0 t0, CP0_STATUS
1878 +
1879 + /* VPEs executing in wait code do not need a stack */
1880 + li t9, KSEG0ADDR(LAUNCH_WAITCODE)
1881 + jr t9
1882 + END(launch_vpe_entry)
1883 +
1884 +/*
1885 + * This function will not be executed in place.
1886 + * It will be copied into memory, and VPEs other than VPE0 will be
1887 + * started to run into this in-memory function.
1888 + */
1889 +LEAF(launch_wait_code)
1890 + .globl launch_wait_code_start
1891 +launch_wait_code_start:
1892 +
1893 + move t0, a0
1894 +
1895 +start_poll:
1896 + /* Poll CPU go flag */
1897 + mtc0 zero, CP0_COUNT
1898 + li t1, LAUNCHPERIOD
1899 + mtc0 t1, CP0_COMPARE
1900 +
1901 +time_wait:
1902 + /* Software wait */
1903 + mfc0 t2, CP0_COUNT
1904 + subu t2, t1
1905 + bltz t2, time_wait
1906 +
1907 + /* Check the launch flag */
1908 + lw t3, LAUNCH_FLAGS(t0)
1909 + and t3, LAUNCH_FGO
1910 + beqz t3, start_poll
1911 +
1912 + /* Reset the counter and interrupts to give naive clients a chance */
1913 + mfc0 t1, CP0_STATUS
1914 + ins t1, zero, STATUSB_IP7, 1
1915 + mtc0 t1, CP0_STATUS
1916 +
1917 + mfc0 t1, CP0_COUNT
1918 + subu t1, 1
1919 + mtc0 t1, CP0_COMPARE
1920 +
1921 + /* Jump to kernel */
1922 + lw t9, LAUNCH_PC(t0)
1923 + lw gp, LAUNCH_GP(t0)
1924 + lw sp, LAUNCH_SP(t0)
1925 + lw a0, LAUNCH_A0(t0)
1926 + move a1, zero
1927 + move a2, zero
1928 + move a3, zero
1929 + ori t3, LAUNCH_FGONE
1930 + sw t3, LAUNCH_FLAGS(t0)
1931 +
1932 + jr t9
1933 +
1934 + .globl launch_wait_code_end
1935 +launch_wait_code_end:
1936 + END(launch_wait_code)
1937 +
1938 +/*
1939 + * Core1 will go here.
1940 + */
1941 +LEAF(launch_core_entry)
1942 + /* Disable caches */
1943 + bal mips_cache_disable
1944 +
1945 + /* Initialize L1 cache only */
1946 + li a0, CONFIG_SYS_ICACHE_SIZE
1947 + li a1, CONFIG_SYS_ICACHE_LINE_SIZE
1948 + li a2, CONFIG_SYS_DCACHE_SIZE
1949 + li a3, CONFIG_SYS_DCACHE_LINE_SIZE
1950 +
1951 + mtc0 zero, CP0_TAGLO
1952 + mtc0 zero, CP0_TAGLO, 2
1953 + ehb
1954 +
1955 + /*
1956 + * Initialize the I-cache first,
1957 + */
1958 + li t0, KSEG0
1959 + addu t1, t0, a0
1960 + /* clear tag to invalidate */
1961 + cache_loop t0, t1, a1, INDEX_STORE_TAG_I
1962 +#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
1963 + /* fill once, so data field parity is correct */
1964 + PTR_LI t0, KSEG0
1965 + cache_loop t0, t1, a1, FILL
1966 + /* invalidate again - prudent but not strictly necessary */
1967 + PTR_LI t0, KSEG0
1968 + cache_loop t0, t1, a1, INDEX_STORE_TAG_I
1969 +#endif
1970 +
1971 + /*
1972 + * then initialize D-cache.
1973 + */
1974 + PTR_LI t0, KSEG0
1975 + PTR_ADDU t1, t0, a2
1976 + /* clear all tags */
1977 + cache_loop t0, t1, a3, INDEX_STORE_TAG_D
1978 +#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
1979 + /* load from each line (in cached space) */
1980 + PTR_LI t0, KSEG0
1981 +2: LONG_L zero, 0(t0)
1982 + PTR_ADDU t0, a3
1983 + bne t0, t1, 2b
1984 + /* clear all tags */
1985 + PTR_LI t0, KSEG0
1986 + cache_loop t0, t1, a3, INDEX_STORE_TAG_D
1987 +#endif
1988 +
1989 + /* Set Cache Mode */
1990 + mfc0 t0, CP0_CONFIG
1991 + li t1, CONF_CM_CACHABLE_COW
1992 + ins t0, t1, 0, 3
1993 + mtc0 t0, CP0_CONFIG
1994 +
1995 + /* Join the coherent domain */
1996 + li a0, 2
1997 + bal join_coherent_domain
1998 +
1999 + /* Bootup Core0/VPE1 */
2000 + bal boot_vpe1
2001 +
2002 + b launch_vpe_entry
2003 + END(launch_core_entry)
2004 +
2005 +/*
2006 + * Bootup VPE1.
2007 + * This subroutine must be executed from VPE0 with VPECONF0[MVP] already set.
2008 + */
2009 +LEAF(boot_vpe1)
2010 + mfc0 t0, CP0_MVPCONF0
2011 +
2012 + /* a0 = number of TCs - 1 */
2013 + ext a0, t0, MVPCONF0_PTC_SHIFT, 8
2014 + beqz a0, _vpe1_init_done
2015 +
2016 + /* a1 = number of VPEs - 1 */
2017 + ext a1, t0, MVPCONF0_PVPE_SHIFT, 4
2018 + beqz a1, _vpe1_init_done
2019 +
2020 + /* a2 = current TC No. */
2021 + move a2, zero
2022 +
2023 + /* Enter VPE Configuration State */
2024 + mfc0 t0, CP0_MVPCONTROL
2025 + or t0, MVPCONTROL_VPC
2026 + mtc0 t0, CP0_MVPCONTROL
2027 + ehb
2028 +
2029 +_next_tc:
2030 + /* Set the TC number to be used on MTTR and MFTR instructions */
2031 + mfc0 t0, CP0_VPECONTROL
2032 + ins t0, a2, 0, 8
2033 + mtc0 t0, CP0_VPECONTROL
2034 + ehb
2035 +
2036 + /* TC0 is already bound */
2037 + beqz a2, _next_vpe
2038 +
2039 + /* Halt current TC */
2040 + li t0, TCHALT_H
2041 + mttc0 t0, CP0_TCHALT
2042 + ehb
2043 +
2044 + /* If there is spare TC, bind it to the last VPE (VPE[a1]) */
2045 + slt t1, a1, a2
2046 + bnez t1, _vpe_bind_tc
2047 + move t1, a1
2048 +
2049 + /* Set Exclusive TC for active TC */
2050 + mftc0 t0, CP0_VPECONF0
2051 + ins t0, a2, VPECONF0_XTC_SHIFT, 8
2052 + mttc0 t0, CP0_VPECONF0
2053 +
2054 + move t1, a2
2055 +_vpe_bind_tc:
2056 + /* Bind TC to a VPE */
2057 + mftc0 t0, CP0_TCBIND
2058 + ins t0, t1, TCBIND_CURVPE_SHIFT, 4
2059 + mttc0 t0, CP0_TCBIND
2060 +
2061 + /*
2062 + * Set up CP0_TCSTATUS register:
2063 + * Disable Coprocessor Usable bits
2064 + * Disable MDMX/DSP ASE
2065 + * Clear Dirty TC
2066 + * not dynamically allocatable
2067 + * not allocated
2068 + * Kernel mode
2069 + * interrupt exempt
2070 + * ASID 0
2071 + */
2072 + li t0, TCSTATUS_IXMT
2073 + mttc0 t0, CP0_TCSTATUS
2074 +
2075 +_next_vpe:
2076 + slt t1, a1, a2
2077 + bnez t1, _done_vpe # No more VPEs
2078 +
2079 + /* Disable TC multi-threading */
2080 + mftc0 t0, CP0_VPECONTROL
2081 + ins t0, zero, VPECONTROL_TE_SHIFT, 1
2082 + mttc0 t0, CP0_VPECONTROL
2083 +
2084 + /* Skip following configuration for TC0 */
2085 + beqz a2, _done_vpe
2086 +
2087 + /* Deactivate VPE, set Master VPE */
2088 + mftc0 t0, CP0_VPECONF0
2089 + ins t0, zero, VPECONF0_VPA_SHIFT, 1
2090 + or t0, VPECONF0_MVP
2091 + mttc0 t0, CP0_VPECONF0
2092 +
2093 + mfc0 t0, CP0_STATUS
2094 + mttc0 t0, CP0_STATUS
2095 +
2096 + mttc0 zero, CP0_EPC
2097 + mttc0 zero, CP0_CAUSE
2098 +
2099 + mfc0 t0, CP0_CONFIG
2100 + mttc0 t0, CP0_CONFIG
2101 +
2102 + /*
2103 + * VPE1 of each core can execute cached as its L1 I$ has already
2104 + * been initialized.
2105 + * and the L2$ has been initialized or "disabled" via CCA override.
2106 + */
2107 + PTR_LA t0, _start
2108 + mttc0 t0, CP0_TCRESTART
2109 +
2110 + /* Unset Interrupt Exempt, set Activate Thread */
2111 + mftc0 t0, CP0_TCSTATUS
2112 + ins t0, zero, TCSTATUS_IXMT_SHIFT, 1
2113 + ori t0, TCSTATUS_A
2114 + mttc0 t0, CP0_TCSTATUS
2115 +
2116 + /* Resume TC */
2117 + mttc0 zero, CP0_TCHALT
2118 +
2119 + /* Activate VPE */
2120 + mftc0 t0, CP0_VPECONF0
2121 + ori t0, VPECONF0_VPA
2122 + mttc0 t0, CP0_VPECONF0
2123 +
2124 +_done_vpe:
2125 + addu a2, 1
2126 + sltu t0, a0, a2
2127 + beqz t0, _next_tc
2128 +
2129 + mfc0 t0, CP0_MVPCONTROL
2130 + /* Enable all activated VPE to execute */
2131 + ori t0, MVPCONTROL_EVP
2132 + /* Exit VPE Configuration State */
2133 + ins t0, zero, MVPCONTROL_VPC_SHIFT, 1
2134 + mtc0 t0, CP0_MVPCONTROL
2135 + ehb
2136 +
2137 +_vpe1_init_done:
2138 + jr ra
2139 + END(boot_vpe1)
2140 --- /dev/null
2141 +++ b/arch/mips/mach-mtmips/mt7621/spl/serial.c
2142 @@ -0,0 +1,24 @@
2143 +// SPDX-License-Identifier: GPL-2.0
2144 +/*
2145 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
2146 + *
2147 + * Author: Weijie Gao <weijie.gao@mediatek.com>
2148 + */
2149 +
2150 +#include <asm/io.h>
2151 +#include "../mt7621.h"
2152 +
2153 +void mtmips_spl_serial_init(void)
2154 +{
2155 +#ifdef CONFIG_SPL_SERIAL
2156 + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
2157 +
2158 +#if CONFIG_CONS_INDEX == 1
2159 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE);
2160 +#elif CONFIG_CONS_INDEX == 2
2161 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M);
2162 +#elif CONFIG_CONS_INDEX == 3
2163 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M);
2164 +#endif /* CONFIG_CONS_INDEX */
2165 +#endif /* CONFIG_SPL_SERIAL */
2166 +}
2167 --- /dev/null
2168 +++ b/arch/mips/mach-mtmips/mt7621/spl/spl.c
2169 @@ -0,0 +1,95 @@
2170 +// SPDX-License-Identifier: GPL-2.0
2171 +/*
2172 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
2173 + *
2174 + * Author: Weijie Gao <weijie.gao@mediatek.com>
2175 + */
2176 +
2177 +#include <spl.h>
2178 +#include <init.h>
2179 +#include <image.h>
2180 +#include <vsprintf.h>
2181 +#include <malloc.h>
2182 +#include <asm/io.h>
2183 +#include <asm/sections.h>
2184 +#include <asm/addrspace.h>
2185 +#include <asm/byteorder.h>
2186 +#include <asm/global_data.h>
2187 +#include <linux/sizes.h>
2188 +#include <mach/serial.h>
2189 +#include "../mt7621.h"
2190 +#include "dram.h"
2191 +
2192 +DECLARE_GLOBAL_DATA_PTR;
2193 +
2194 +struct tpl_info {
2195 + u32 magic;
2196 + u32 size;
2197 +};
2198 +
2199 +void set_timer_freq_simple(void)
2200 +{
2201 + u32 div = get_xtal_mhz();
2202 +
2203 + /* Round down cpu freq */
2204 + gd->arch.timer_freq = rounddown(CONFIG_MT7621_CPU_FREQ, div) * 500000;
2205 +}
2206 +
2207 +void __noreturn board_init_f(ulong dummy)
2208 +{
2209 + spl_init();
2210 +
2211 +#ifdef CONFIG_SPL_SERIAL
2212 + /*
2213 + * mtmips_spl_serial_init() is useful if debug uart is enabled,
2214 + * or DM based serial is not enabled.
2215 + */
2216 + mtmips_spl_serial_init();
2217 + preloader_console_init();
2218 +#endif
2219 +
2220 + board_init_r(NULL, 0);
2221 +}
2222 +
2223 +void board_boot_order(u32 *spl_boot_list)
2224 +{
2225 +#ifdef CONFIG_MT7621_BOOT_FROM_NAND
2226 + spl_boot_list[0] = BOOT_DEVICE_NAND;
2227 +#else
2228 + spl_boot_list[0] = BOOT_DEVICE_NOR;
2229 +#endif
2230 +}
2231 +
2232 +unsigned long spl_nor_get_uboot_base(void)
2233 +{
2234 + const struct tpl_info *tpli;
2235 + const image_header_t *hdr;
2236 + u32 addr;
2237 +
2238 + addr = FLASH_MMAP_BASE + TPL_INFO_OFFSET;
2239 + tpli = (const struct tpl_info *)KSEG1ADDR(addr);
2240 +
2241 + if (tpli->magic == TPL_INFO_MAGIC) {
2242 + addr = FLASH_MMAP_BASE + tpli->size;
2243 + hdr = (const image_header_t *)KSEG1ADDR(addr);
2244 +
2245 + if (image_get_magic(hdr) == IH_MAGIC) {
2246 + addr += sizeof(*hdr) + image_get_size(hdr);
2247 + return KSEG1ADDR(addr);
2248 + }
2249 + }
2250 +
2251 + panic("Unable to locate SPL payload\n");
2252 + return 0;
2253 +}
2254 +
2255 +uint32_t spl_nand_get_uboot_raw_page(void)
2256 +{
2257 + const struct stage_header *sh = (const struct stage_header *)&_start;
2258 + u32 addr;
2259 +
2260 + addr = image_get_header_size() + be32_to_cpu(sh->stage_size);
2261 + addr = ALIGN(addr, SZ_4K);
2262 +
2263 + return addr;
2264 +}
2265 --- /dev/null
2266 +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S
2267 @@ -0,0 +1,226 @@
2268 +/* SPDX-License-Identifier: GPL-2.0 */
2269 +/*
2270 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
2271 + *
2272 + * Author: Weijie Gao <weijie.gao@mediatek.com>
2273 + */
2274 +
2275 +#include <asm-offsets.h>
2276 +#include <config.h>
2277 +#include <asm/asm.h>
2278 +#include <asm/regdef.h>
2279 +#include <asm/mipsregs.h>
2280 +#include <asm/cacheops.h>
2281 +#include <asm/addrspace.h>
2282 +#include <asm/mipsmtregs.h>
2283 +#include <asm/cm.h>
2284 +#include "../mt7621.h"
2285 +#include "dram.h"
2286 +
2287 +#ifndef CONFIG_SYS_INIT_SP_ADDR
2288 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
2289 + CONFIG_SYS_INIT_SP_OFFSET)
2290 +#endif
2291 +
2292 +#define SP_ADDR_TEMP 0xbe10dff0
2293 +
2294 + .macro init_wr sel
2295 + MTC0 zero, CP0_WATCHLO,\sel
2296 + mtc0 t1, CP0_WATCHHI,\sel
2297 + .endm
2298 +
2299 + .macro setup_stack_gd
2300 + li t0, -16
2301 + PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
2302 + and sp, t1, t0 # force 16 byte alignment
2303 + PTR_SUBU \
2304 + sp, sp, GD_SIZE # reserve space for gd
2305 + and sp, sp, t0 # force 16 byte alignment
2306 + move k0, sp # save gd pointer
2307 +#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
2308 + !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
2309 + li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
2310 + PTR_SUBU \
2311 + sp, sp, t2 # reserve space for early malloc
2312 + and sp, sp, t0 # force 16 byte alignment
2313 +#endif
2314 + move fp, sp
2315 +
2316 + /* Clear gd */
2317 + move t0, k0
2318 +1:
2319 + PTR_S zero, 0(t0)
2320 + PTR_ADDIU t0, PTRSIZE
2321 + blt t0, t1, 1b
2322 + nop
2323 +
2324 +#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
2325 + !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
2326 + PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
2327 +#endif
2328 + .endm
2329 +
2330 + .set noreorder
2331 +
2332 +ENTRY(_start)
2333 + b 1f
2334 + mtc0 zero, CP0_COUNT
2335 +
2336 + /* Stage header required by BootROM */
2337 + .org 0x8
2338 + .word 0 # ep, filled by mkimage
2339 + .word 0 # stage_size, filled by mkimage
2340 + .word 0 # has_stage2
2341 + .word 0 # next_ep
2342 + .word 0 # next_size
2343 + .word 0 # next_offset
2344 +
2345 +1:
2346 + /* Init CP0 Status */
2347 + mfc0 t0, CP0_STATUS
2348 + and t0, ST0_IMPL
2349 + or t0, ST0_BEV | ST0_ERL
2350 + mtc0 t0, CP0_STATUS
2351 + ehb
2352 +
2353 + /* Clear Watch Status bits and disable watch exceptions */
2354 + li t1, 0x7 # Clear I, R and W conditions
2355 + init_wr 0
2356 + init_wr 1
2357 + init_wr 2
2358 + init_wr 3
2359 +
2360 + /* Clear WP, IV and SW interrupts */
2361 + mtc0 zero, CP0_CAUSE
2362 +
2363 + /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
2364 + mtc0 zero, CP0_COMPARE
2365 +
2366 + /* VPE1 goes to wait code directly */
2367 + mfc0 t0, CP0_TCBIND
2368 + andi t0, TCBIND_CURVPE
2369 + bnez t0, launch_vpe_entry
2370 + nop
2371 +
2372 + /* Core1 goes to specific launch entry */
2373 + PTR_LI t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE)
2374 + lw t1, GCR_Cx_ID(t0)
2375 + bnez t1, launch_core_entry
2376 + nop
2377 +
2378 + /* MT7530 reset */
2379 + li t0, KSEG1ADDR(SYSCTL_BASE)
2380 + lw t1, SYSCTL_RSTCTL_REG(t0)
2381 + ori t1, MCM_RST
2382 + sw t1, SYSCTL_RSTCTL_REG(t0)
2383 +
2384 + /* Disable DMA route for PSE SRAM set by BootROM */
2385 + PTR_LI t0, KSEG1ADDR(DMA_CFG_ARB_BASE)
2386 + sw zero, DMA_ROUTE_REG(t0)
2387 +
2388 + /* Set CPU clock to 500MHz (Required if boot from NAND) */
2389 + li t0, KSEG1ADDR(SYSCTL_BASE)
2390 + lw t1, SYSCTL_CLKCFG0_REG(t0)
2391 + ins t1, zero, 30, 2 # CPU_CLK_SEL
2392 + sw t1, SYSCTL_CLKCFG0_REG(t0)
2393 +
2394 + /* Set CPU clock divider to 1/1 */
2395 + li t0, KSEG1ADDR(RBUS_BASE)
2396 + li t1, 0x101
2397 + sw t1, RBUS_DYN_CFG0_REG(t0)
2398 +
2399 + /* (Re-)initialize the SRAM */
2400 + bal mips_sram_init
2401 + nop
2402 +
2403 + /* Set up temporary stack */
2404 + li sp, SP_ADDR_TEMP
2405 +
2406 + /* Setup full CPS */
2407 + bal mips_cm_map
2408 + nop
2409 +
2410 + bal mt7621_cps_init
2411 + nop
2412 +
2413 + /* Prepare for CPU/DDR initialization binary blob */
2414 + bal prepare_stage_bin
2415 + nop
2416 +
2417 + /* Call CPU/DDR initialization binary blob */
2418 + li t9, STAGE_LOAD_ADDR
2419 + jalr t9
2420 + nop
2421 +
2422 + /* Switch CPU PLL source */
2423 + li t0, KSEG1ADDR(SYSCTL_BASE)
2424 + lw t1, SYSCTL_CLKCFG0_REG(t0)
2425 + li t2, 1
2426 + ins t1, t2, CPU_CLK_SEL_S, 2
2427 + sw t1, SYSCTL_CLKCFG0_REG(t0)
2428 +
2429 + /*
2430 + * Currently SPL is running on locked L2 cache (on KSEG0).
2431 + * To reset the entire cache, we have to writeback SPL to DRAM first.
2432 + * Cache flush won't work here. Use memcpy instead.
2433 + */
2434 +
2435 + la a0, __text_start
2436 + move a1, a0
2437 + la a2, __image_copy_end
2438 + sub a2, a2, a1
2439 + li a3, 5
2440 + ins a0, a3, 29, 3 # convert to KSEG1
2441 +
2442 + bal memcpy
2443 + nop
2444 +
2445 + /* Disable caches */
2446 + bal mips_cache_disable
2447 + nop
2448 +
2449 + /* Reset caches */
2450 + bal mips_cache_reset
2451 + nop
2452 +
2453 + /* Disable SRAM */
2454 + li t0, KSEG1ADDR(FE_BASE)
2455 + li t1, FE_PSE_RESET
2456 + sw t1, FE_RST_GLO_REG(t0)
2457 +
2458 + /* Clear the .bss section */
2459 + la a0, __bss_start
2460 + la a1, __bss_end
2461 +1: sw zero, 0(a0)
2462 + addiu a0, 4
2463 + ble a0, a1, 1b
2464 + nop
2465 +
2466 + /* Set up initial stack and global data */
2467 + setup_stack_gd
2468 +
2469 +#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
2470 + /* Set malloc base */
2471 + li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
2472 + PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset
2473 +#endif
2474 +
2475 +#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_SPL_SERIAL)
2476 + /* Earliest point to set up debug uart */
2477 + bal debug_uart_init
2478 + nop
2479 +#endif
2480 +
2481 + /* Setup timer */
2482 + bal set_timer_freq_simple
2483 + nop
2484 +
2485 + /* Bootup secondary CPUs */
2486 + bal secondary_cpu_init
2487 + nop
2488 +
2489 + move a0, zero # a0 <-- boot_flags = 0
2490 + bal board_init_f
2491 + move ra, zero
2492 +
2493 + END(_start)
2494 --- /dev/null
2495 +++ b/arch/mips/mach-mtmips/mt7621/sram_init.S
2496 @@ -0,0 +1,22 @@
2497 +/* SPDX-License-Identifier: GPL-2.0 */
2498 +/*
2499 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
2500 + *
2501 + * Author: Weijie Gao <weijie.gao@mediatek.com>
2502 + */
2503 +
2504 +#include <asm/addrspace.h>
2505 +#include <asm/asm.h>
2506 +#include <asm/regdef.h>
2507 +#include "mt7621.h"
2508 +
2509 +LEAF(mips_sram_init)
2510 + li t0, KSEG1ADDR(FE_BASE)
2511 + li t1, FE_PSE_RESET
2512 + sw t1, FE_RST_GLO_REG(t0)
2513 +
2514 + li t1, (FE_PSE_RAM | FE_PSE_MEM_EN)
2515 + sw t1, FE_RST_GLO_REG(t0)
2516 +
2517 + jr ra
2518 + END(mips_sram_init)
2519 --- /dev/null
2520 +++ b/arch/mips/mach-mtmips/mt7621/tpl/Makefile
2521 @@ -0,0 +1,4 @@
2522 +
2523 +extra-y += start.o
2524 +
2525 +obj-y += tpl.o
2526 --- /dev/null
2527 +++ b/arch/mips/mach-mtmips/mt7621/tpl/start.S
2528 @@ -0,0 +1,161 @@
2529 +/* SPDX-License-Identifier: GPL-2.0 */
2530 +/*
2531 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
2532 + *
2533 + * Author: Weijie Gao <weijie.gao@mediatek.com>
2534 + */
2535 +
2536 +#include <asm-offsets.h>
2537 +#include <config.h>
2538 +#include <asm/asm.h>
2539 +#include <asm/regdef.h>
2540 +#include <asm/addrspace.h>
2541 +#include <asm/mipsregs.h>
2542 +#include <asm/cm.h>
2543 +#include "../mt7621.h"
2544 +
2545 +#define SP_ADDR_TEMP 0xbe10dff0
2546 +
2547 + .set noreorder
2548 +
2549 + .macro init_wr sel
2550 + MTC0 zero, CP0_WATCHLO,\sel
2551 + mtc0 t1, CP0_WATCHHI,\sel
2552 + .endm
2553 +
2554 + .macro uhi_mips_exception
2555 + move k0, t9 # preserve t9 in k0
2556 + move k1, a0 # preserve a0 in k1
2557 + li t9, 15 # UHI exception operation
2558 + li a0, 0 # Use hard register context
2559 + sdbbp 1 # Invoke UHI operation
2560 + .endm
2561 +
2562 +ENTRY(_start)
2563 + b reset
2564 + mtc0 zero, CP0_COUNT
2565 +
2566 + /*
2567 + * Store TPL size here.
2568 + * This will be used by SPL to locate u-boot payload.
2569 + */
2570 + .org TPL_INFO_OFFSET
2571 + .word TPL_INFO_MAGIC
2572 + .word __image_copy_len
2573 +
2574 + /* Exception vector */
2575 + .org 0x200
2576 + /* TLB refill, 32 bit task */
2577 + uhi_mips_exception
2578 +
2579 + .org 0x280
2580 + /* XTLB refill, 64 bit task */
2581 + uhi_mips_exception
2582 +
2583 + .org 0x300
2584 + /* Cache error exception */
2585 + uhi_mips_exception
2586 +
2587 + .org 0x380
2588 + /* General exception */
2589 + uhi_mips_exception
2590 +
2591 + .org 0x400
2592 + /* Catch interrupt exceptions */
2593 + uhi_mips_exception
2594 +
2595 + .org 0x480
2596 + /* EJTAG debug exception */
2597 +1: b 1b
2598 + nop
2599 +
2600 + .org 0x500
2601 +
2602 +reset:
2603 + /* Set KSEG0 to Uncached */
2604 + mfc0 t0, CP0_CONFIG
2605 + ins t0, zero, 0, 3
2606 + ori t0, t0, CONF_CM_UNCACHED
2607 + mtc0 t0, CP0_CONFIG
2608 + ehb
2609 +
2610 + /* Check for CPU number */
2611 + mfc0 t0, CP0_EBASE
2612 + and t0, t0, MIPS_EBASE_CPUNUM
2613 + beqz t0, 1f
2614 + nop
2615 +
2616 + /* Secondary core goes to specified SPL entry address */
2617 + li t0, KSEG1ADDR(SYSCTL_BASE)
2618 + lw t0, BOOT_SRAM_BASE_REG(t0)
2619 + jr t0
2620 + nop
2621 +
2622 + /* Init CP0 Status */
2623 +1: mfc0 t0, CP0_STATUS
2624 + and t0, ST0_IMPL
2625 + or t0, ST0_BEV | ST0_ERL
2626 + mtc0 t0, CP0_STATUS
2627 + nop
2628 +
2629 + /* Clear Watch Status bits and disable watch exceptions */
2630 + li t1, 0x7 # Clear I, R and W conditions
2631 + init_wr 0
2632 + init_wr 1
2633 + init_wr 2
2634 + init_wr 3
2635 +
2636 + /* Clear WP, IV and SW interrupts */
2637 + mtc0 zero, CP0_CAUSE
2638 +
2639 + /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
2640 + mtc0 zero, CP0_COMPARE
2641 +
2642 + /* Setup basic CPS */
2643 + bal mips_cm_map
2644 + nop
2645 +
2646 + li t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE)
2647 + li t1, GCR_REG0_BASE_VALUE
2648 + sw t1, GCR_REG0_BASE(t0)
2649 +
2650 + li t1, ((GCR_REG0_MASK_VALUE << GCR_REGn_MASK_ADDRMASK_SHIFT) | \
2651 + GCR_REGn_MASK_CMTGT_IOCU0)
2652 + sw t1, GCR_REG0_MASK(t0)
2653 +
2654 + lw t1, GCR_BASE(t0)
2655 + ins t1, zero, 0, 2 # CM_DEFAULT_TARGET
2656 + sw t1, GCR_BASE(t0)
2657 +
2658 + lw t1, GCR_CONTROL(t0)
2659 + li t2, GCR_CONTROL_SYNCCTL
2660 + or t1, t1, t2
2661 + sw t1, GCR_CONTROL(t0)
2662 +
2663 + /* Increase SPI frequency */
2664 + li t0, KSEG1ADDR(SPI_BASE)
2665 + li t1, 5
2666 + sw t1, SPI_SPACE_REG(t0)
2667 +
2668 + /* Set CPU clock to 500MHz */
2669 + li t0, KSEG1ADDR(SYSCTL_BASE)
2670 + lw t1, SYSCTL_CLKCFG0_REG(t0)
2671 + ins t1, zero, 30, 2 # CPU_CLK_SEL
2672 + sw t1, SYSCTL_CLKCFG0_REG(t0)
2673 +
2674 + /* Set CPU clock divider to 1/1 */
2675 + li t0, KSEG1ADDR(RBUS_BASE)
2676 + li t1, 0x101
2677 + sw t1, RBUS_DYN_CFG0_REG(t0)
2678 +
2679 + /* Initialize the SRAM */
2680 + bal mips_sram_init
2681 + nop
2682 +
2683 + /* Set up initial stack */
2684 + li sp, SP_ADDR_TEMP
2685 +
2686 + bal tpl_main
2687 + nop
2688 +
2689 + END(_start)
2690 --- /dev/null
2691 +++ b/arch/mips/mach-mtmips/mt7621/tpl/tpl.c
2692 @@ -0,0 +1,144 @@
2693 +// SPDX-License-Identifier: GPL-2.0
2694 +/*
2695 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
2696 + *
2697 + * Author: Weijie Gao <weijie.gao@mediatek.com>
2698 + */
2699 +
2700 +#include <image.h>
2701 +#include <asm/system.h>
2702 +#include <asm/sections.h>
2703 +#include <asm/cacheops.h>
2704 +#include <asm/mipsregs.h>
2705 +#include <asm/cm.h>
2706 +
2707 +#define INDEX_STORE_DATA_SD 0x0f
2708 +
2709 +typedef void __noreturn (*image_entry_noargs_t)(void);
2710 +
2711 +/*
2712 + * Lock L2 cache and fill data
2713 + * Assume that data is 4-byte aligned and start_addr/size is 32-byte aligned
2714 + */
2715 +static void fill_lock_l2cache(uintptr_t dataptr, ulong start_addr, ulong size)
2716 +{
2717 + ulong slsize = CONFIG_SYS_DCACHE_LINE_SIZE;
2718 + ulong end_addr = start_addr + size;
2719 + const u32 *data = (u32 *)dataptr;
2720 + ulong i, addr;
2721 + u32 val;
2722 +
2723 + /* Clear WSC & SPR bit in ErrCtl */
2724 + val = read_c0_ecc();
2725 + val &= 0xcfffffff;
2726 + write_c0_ecc(val);
2727 + execution_hazard_barrier();
2728 +
2729 + for (addr = start_addr; addr < end_addr; addr += slsize) {
2730 + /* Set STagLo to lock cache line */
2731 + write_c0_staglo((addr & 0x1ffff800) | 0xa0);
2732 + mips_cache(INDEX_STORE_TAG_SD, (void *)addr);
2733 +
2734 + /* Fill data */
2735 + for (i = 0; i < slsize; i += 8) {
2736 + val = *data++;
2737 + __write_32bit_c0_register($28, 5, val); /* sdtaglo */
2738 + val = *data++;
2739 + __write_32bit_c0_register($29, 5, val); /* sdtaghi */
2740 + mips_cache(INDEX_STORE_DATA_SD, (void *)(addr + i));
2741 + }
2742 + }
2743 +
2744 + sync();
2745 +}
2746 +
2747 +/* A simple function to initialize MT7621's cache */
2748 +static void mt7621_cache_init(void)
2749 +{
2750 + void __iomem *cm_base = (void *)KSEG1ADDR(CONFIG_MIPS_CM_BASE);
2751 + ulong lsize = CONFIG_SYS_DCACHE_LINE_SIZE;
2752 + ulong addr;
2753 + u32 val;
2754 +
2755 + /* Enable CCA override. Set to uncached */
2756 + val = readl(cm_base + GCR_BASE);
2757 + val &= ~CCA_DEFAULT_OVR_MASK;
2758 + val |= CCA_DEFAULT_OVREN | (2 << CCA_DEFAULT_OVR_SHIFT);
2759 + writel(val, cm_base + GCR_BASE);
2760 +
2761 + /* Initialize L1 I-Cache */
2762 + write_c0_taglo(0);
2763 + write_c0_taghi(0);
2764 +
2765 + for (addr = 0; addr < CONFIG_SYS_ICACHE_SIZE; addr += lsize)
2766 + mips_cache(INDEX_STORE_TAG_I, (void *)addr);
2767 +
2768 + /* Initialize L1 D-Cache */
2769 + write_c0_dtaglo(0);
2770 + __write_32bit_c0_register($29, 2, 0); /* dtaghi */
2771 +
2772 + for (addr = 0; addr < CONFIG_SYS_DCACHE_SIZE; addr += lsize)
2773 + mips_cache(INDEX_STORE_TAG_D, (void *)addr);
2774 +
2775 + /* Initialize L2 Cache */
2776 + write_c0_staglo(0);
2777 + __write_32bit_c0_register($29, 4, 0); /* staghi */
2778 +
2779 + for (addr = 0; addr < (256 << 10); addr += lsize)
2780 + mips_cache(INDEX_STORE_TAG_SD, (void *)addr);
2781 +
2782 + /* Dsiable CCA override */
2783 + val = readl(cm_base + GCR_BASE);
2784 + val &= ~(CCA_DEFAULT_OVR_MASK | CCA_DEFAULT_OVREN);
2785 + writel(val, cm_base + GCR_BASE);
2786 +
2787 + /* Set KSEG0 to non-coherent cached (important!) */
2788 + val = read_c0_config();
2789 + val &= ~CONF_CM_CMASK;
2790 + val |= CONF_CM_CACHABLE_NONCOHERENT;
2791 + write_c0_config(val);
2792 + execution_hazard_barrier();
2793 +
2794 + /* Again, invalidate L1 D-Cache */
2795 + for (addr = 0; addr < CONFIG_SYS_DCACHE_SIZE; addr += lsize)
2796 + mips_cache(INDEX_WRITEBACK_INV_D, (void *)addr);
2797 +
2798 + /* Invalidate L1 I-Cache */
2799 + for (addr = 0; addr < CONFIG_SYS_ICACHE_SIZE; addr += lsize)
2800 + mips_cache(INDEX_INVALIDATE_I, (void *)addr);
2801 +
2802 + /* Disable L2 cache bypass */
2803 + val = read_c0_config2();
2804 + val &= ~MIPS_CONF_IMPL;
2805 + write_c0_config2(val);
2806 + execution_hazard_barrier();
2807 +}
2808 +
2809 +void __noreturn tpl_main(void)
2810 +{
2811 + const image_header_t *hdr = (const image_header_t *)__image_copy_end;
2812 + image_entry_noargs_t image_entry;
2813 + u32 loadaddr, size;
2814 + uintptr_t data;
2815 +
2816 + /* Initialize the cache first */
2817 + mt7621_cache_init();
2818 +
2819 + if (image_get_magic(hdr) != IH_MAGIC)
2820 + goto failed;
2821 +
2822 + loadaddr = image_get_load(hdr);
2823 + size = image_get_size(hdr);
2824 + image_entry = (image_entry_noargs_t)image_get_ep(hdr);
2825 +
2826 + /* Load TPL image to L2 cache */
2827 + data = (uintptr_t)__image_copy_end + sizeof(struct image_header);
2828 + fill_lock_l2cache(data, loadaddr, size);
2829 +
2830 + /* Jump to SPL */
2831 + image_entry();
2832 +
2833 +failed:
2834 + for (;;)
2835 + ;
2836 +}
2837 --- /dev/null
2838 +++ b/include/configs/mt7621.h
2839 @@ -0,0 +1,65 @@
2840 +/* SPDX-License-Identifier: GPL-2.0 */
2841 +/*
2842 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
2843 + *
2844 + * Author: Weijie Gao <weijie.gao@mediatek.com>
2845 + */
2846 +
2847 +#ifndef __CONFIG_MT7621_H
2848 +#define __CONFIG_MT7621_H
2849 +
2850 +#define CONFIG_SYS_MIPS_TIMER_FREQ 440000000
2851 +
2852 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
2853 +
2854 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
2855 +
2856 +#define CONFIG_VERY_BIG_RAM
2857 +#define CONFIG_MAX_MEM_MAPPED 0x1c000000
2858 +
2859 +#define CONFIG_SYS_INIT_SP_OFFSET 0x800000
2860 +
2861 +#define CONFIG_SYS_BOOTM_LEN 0x2000000
2862 +
2863 +#define CONFIG_SYS_MAXARGS 16
2864 +#define CONFIG_SYS_CBSIZE 1024
2865 +
2866 +#define CONFIG_SYS_NONCACHED_MEMORY 0x100000
2867 +
2868 +/* MMC */
2869 +#define MMC_SUPPORTS_TUNING
2870 +
2871 +/* NAND */
2872 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
2873 +
2874 +/* Serial SPL */
2875 +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
2876 +#define CONFIG_SYS_NS16550_MEM32
2877 +#define CONFIG_SYS_NS16550_CLK 50000000
2878 +#define CONFIG_SYS_NS16550_REG_SIZE -4
2879 +#define CONFIG_SYS_NS16550_COM1 0xbe000c00
2880 +#endif
2881 +
2882 +/* Serial common */
2883 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
2884 + 230400, 460800, 921600 }
2885 +
2886 +/* SPL */
2887 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
2888 +
2889 +#ifdef CONFIG_TPL_BUILD
2890 +#define CONFIG_SPL_START_S_PATH "arch/mips/mach-mtmips/mt7621/tpl"
2891 +/* .bss will not be used by TPL */
2892 +#define CONFIG_SPL_BSS_START_ADDR 0x80000000
2893 +#define CONFIG_SPL_BSS_MAX_SIZE 0
2894 +#else
2895 +#define CONFIG_SPL_START_S_PATH "arch/mips/mach-mtmips/mt7621/spl"
2896 +#define CONFIG_SPL_BSS_START_ADDR 0x80140000
2897 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
2898 +#define CONFIG_SPL_MAX_SIZE 0x30000
2899 +#endif
2900 +
2901 +/* Dummy value */
2902 +#define CONFIG_SYS_UBOOT_BASE 0
2903 +
2904 +#endif /* __CONFIG_MT7621_H */
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