e71ff0923c8329491afa25a1abba447786d7e408
[openwrt/staging/wigyori.git] /
1 From 4d572e867bdb372bb4add39a0fa495c6a9c9a8da Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Wed, 8 May 2024 11:43:56 +0100
4 Subject: [PATCH] net: ethernet: mediatek: use ADMAv1 instead of ADMAv2.0 on
5 MT7981 and MT7986
6
7 ADMAv2.0 is plagued by RX hangs which can't easily detected and happen upon
8 receival of a corrupted Ethernet frame.
9
10 Use ADMAv1 instead which is also still present and usable, and doesn't
11 suffer from that problem.
12
13 Fixes: 197c9e9b17b1 ("net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset")
14 Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
15 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
16 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
17 Link: https://lore.kernel.org/r/57cef74bbd0c243366ad1ff4221e3f72f437ec80.1715164770.git.daniel@makrotopia.org
18 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
19 ---
20 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
21 1 file changed, 23 insertions(+), 23 deletions(-)
22
23 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
24 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
25 @@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
26 .tx_irq_mask = 0x461c,
27 .tx_irq_status = 0x4618,
28 .pdma = {
29 - .rx_ptr = 0x6100,
30 - .rx_cnt_cfg = 0x6104,
31 - .pcrx_ptr = 0x6108,
32 - .glo_cfg = 0x6204,
33 - .rst_idx = 0x6208,
34 - .delay_irq = 0x620c,
35 - .irq_status = 0x6220,
36 - .irq_mask = 0x6228,
37 - .adma_rx_dbg0 = 0x6238,
38 - .int_grp = 0x6250,
39 + .rx_ptr = 0x4100,
40 + .rx_cnt_cfg = 0x4104,
41 + .pcrx_ptr = 0x4108,
42 + .glo_cfg = 0x4204,
43 + .rst_idx = 0x4208,
44 + .delay_irq = 0x420c,
45 + .irq_status = 0x4220,
46 + .irq_mask = 0x4228,
47 + .adma_rx_dbg0 = 0x4238,
48 + .int_grp = 0x4250,
49 },
50 .qdma = {
51 .qtx_cfg = 0x4400,
52 @@ -1106,7 +1106,7 @@ static bool mtk_rx_get_desc(struct mtk_e
53 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
54 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
55 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
56 - if (mtk_is_netsys_v2_or_greater(eth)) {
57 + if (mtk_is_netsys_v3_or_greater(eth)) {
58 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
59 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
60 }
61 @@ -2024,7 +2024,7 @@ static int mtk_poll_rx(struct napi_struc
62 break;
63
64 /* find out which mac the packet come from. values start at 1 */
65 - if (mtk_is_netsys_v2_or_greater(eth)) {
66 + if (mtk_is_netsys_v3_or_greater(eth)) {
67 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
68
69 switch (val) {
70 @@ -2136,7 +2136,7 @@ static int mtk_poll_rx(struct napi_struc
71 skb->dev = netdev;
72 bytes += skb->len;
73
74 - if (mtk_is_netsys_v2_or_greater(eth)) {
75 + if (mtk_is_netsys_v3_or_greater(eth)) {
76 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
77 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
78 if (hash != MTK_RXD5_FOE_ENTRY)
79 @@ -2686,7 +2686,7 @@ static int mtk_rx_alloc(struct mtk_eth *
80
81 rxd->rxd3 = 0;
82 rxd->rxd4 = 0;
83 - if (mtk_is_netsys_v2_or_greater(eth)) {
84 + if (mtk_is_netsys_v3_or_greater(eth)) {
85 rxd->rxd5 = 0;
86 rxd->rxd6 = 0;
87 rxd->rxd7 = 0;
88 @@ -3889,7 +3889,7 @@ static int mtk_hw_init(struct mtk_eth *e
89 else
90 mtk_hw_reset(eth);
91
92 - if (mtk_is_netsys_v2_or_greater(eth)) {
93 + if (mtk_is_netsys_v3_or_greater(eth)) {
94 /* Set FE to PDMAv2 if necessary */
95 val = mtk_r32(eth, MTK_FE_GLO_MISC);
96 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
97 @@ -5167,11 +5167,11 @@ static const struct mtk_soc_data mt7981_
98 .dma_len_offset = 8,
99 },
100 .rx = {
101 - .desc_size = sizeof(struct mtk_rx_dma_v2),
102 - .irq_done_mask = MTK_RX_DONE_INT_V2,
103 + .desc_size = sizeof(struct mtk_rx_dma),
104 + .irq_done_mask = MTK_RX_DONE_INT,
105 .dma_l4_valid = RX_DMA_L4_VALID_V2,
106 - .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
107 - .dma_len_offset = 8,
108 + .dma_max_len = MTK_TX_DMA_BUF_LEN,
109 + .dma_len_offset = 16,
110 },
111 };
112
113 @@ -5193,11 +5193,11 @@ static const struct mtk_soc_data mt7986_
114 .dma_len_offset = 8,
115 },
116 .rx = {
117 - .desc_size = sizeof(struct mtk_rx_dma_v2),
118 - .irq_done_mask = MTK_RX_DONE_INT_V2,
119 + .desc_size = sizeof(struct mtk_rx_dma),
120 + .irq_done_mask = MTK_RX_DONE_INT,
121 .dma_l4_valid = RX_DMA_L4_VALID_V2,
122 - .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
123 - .dma_len_offset = 8,
124 + .dma_max_len = MTK_TX_DMA_BUF_LEN,
125 + .dma_len_offset = 16,
126 },
127 };
128