git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Sat, 5 Nov 2022 23:36:16 +0100
   4 Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX
   5  Wireless Ethernet Dispatch
   6
   7 Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
   8 Dispatch to offload traffic received by the wlan interface to lan/wan
   9 one.
  10
  11 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
  12 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
  13 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  14 Signed-off-by: David S. Miller <davem@davemloft.net>
  15 ---
  16  arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++
  17  1 file changed, 65 insertions(+)
  18
  19 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
  20 +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
  21 @@ -76,6 +76,47 @@
  22                         no-map;
  23                         reg = <0 0x4fc00000 0 0x00100000>;
  24                 };
  25 +
  26 +               wo_emi0: wo-emi@4fd00000 {
  27 +                       reg = <0 0x4fd00000 0 0x40000>;
  28 +                       no-map;
  29 +               };
  30 +
  31 +               wo_emi1: wo-emi@4fd40000 {
  32 +                       reg = <0 0x4fd40000 0 0x40000>;
  33 +                       no-map;
  34 +               };
  35 +
  36 +               wo_ilm0: wo-ilm@151e0000 {
  37 +                       reg = <0 0x151e0000 0 0x8000>;
  38 +                       no-map;
  39 +               };
  40 +
  41 +               wo_ilm1: wo-ilm@151f0000 {
  42 +                       reg = <0 0x151f0000 0 0x8000>;
  43 +                       no-map;
  44 +               };
  45 +
  46 +               wo_data: wo-data@4fd80000 {
  47 +                       reg = <0 0x4fd80000 0 0x240000>;
  48 +                       no-map;
  49 +               };
  50 +
  51 +               wo_dlm0: wo-dlm@151e8000 {
  52 +                       reg = <0 0x151e8000 0 0x2000>;
  53 +                       no-map;
  54 +               };
  55 +
  56 +               wo_dlm1: wo-dlm@151f8000 {
  57 +                       reg = <0 0x151f8000 0 0x2000>;
  58 +                       no-map;
  59 +               };
  60 +
  61 +               wo_boot: wo-boot@15194000 {
  62 +                       reg = <0 0x15194000 0 0x1000>;
  63 +                       no-map;
  64 +               };
  65 +
  66         };
  67
  68         timer {
  69 @@ -240,6 +281,11 @@
  70                         reg = <0 0x15010000 0 0x1000>;
  71                         interrupt-parent = <&gic>;
  72                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
  73 +                       memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
  74 +                                       <&wo_data>, <&wo_boot>;
  75 +                       memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
  76 +                                             "wo-data", "wo-boot";
  77 +                       mediatek,wo-ccif = <&wo_ccif0>;
  78                 };
  79
  80                 wed1: wed@15011000 {
  81 @@ -248,6 +294,25 @@
  82                         reg = <0 0x15011000 0 0x1000>;
  83                         interrupt-parent = <&gic>;
  84                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
  85 +                       memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
  86 +                                       <&wo_data>, <&wo_boot>;
  87 +                       memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
  88 +                                             "wo-data", "wo-boot";
  89 +                       mediatek,wo-ccif = <&wo_ccif1>;
  90 +               };
  91 +
  92 +               wo_ccif0: syscon@151a5000 {
  93 +                       compatible = "mediatek,mt7986-wo-ccif", "syscon";
  94 +                       reg = <0 0x151a5000 0 0x1000>;
  95 +                       interrupt-parent = <&gic>;
  96 +                       interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
  97 +               };
  98 +
  99 +               wo_ccif1: syscon@151ad000 {
 100 +                       compatible = "mediatek,mt7986-wo-ccif", "syscon";
 101 +                       reg = <0 0x151ad000 0 0x1000>;
 102 +                       interrupt-parent = <&gic>;
 103 +                       interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 104                 };
 105
 106                 eth: ethernet@15100000 {