git.openwrt.org Git - openwrt/staging/981213.git/blob

   1 From 64b2d6ffff862c0e7278198b4229e42e1abb3bb1 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Mon, 10 Jan 2022 12:49:30 +0100
   4 Subject: [PATCH 2/2] staging: mt7621-dts: align resets with binding documentation
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
  10 to be used as a reset provider. Align reset related bits and system controller
  11 node with binding documentation along the dtsi file.
  12
  13 Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  14 Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
  15 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  16 Link: https://lore.kernel.org/r/20220110114930.1406665-5-sergio.paracuellos@gmail.com
  17 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  18 ---
  19  drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------
  20  1 file changed, 9 insertions(+), 12 deletions(-)
  21
  22 --- a/drivers/staging/mt7621-dts/mt7621.dtsi
  23 +++ b/drivers/staging/mt7621-dts/mt7621.dtsi
  24 @@ -1,6 +1,7 @@
  25  #include <dt-bindings/interrupt-controller/mips-gic.h>
  26  #include <dt-bindings/gpio/gpio.h>
  27  #include <dt-bindings/clock/mt7621-clk.h>
  28 +#include <dt-bindings/reset/mt7621-reset.h>
  29
  30  / {
  31         #address-cells = <1>;
  32 @@ -59,6 +60,7 @@
  33                         compatible = "mediatek,mt7621-sysc", "syscon";
  34                         reg = <0x0 0x100>;
  35                         #clock-cells = <1>;
  36 +                       #reset-cells = <1>;
  37                         ralink,memctl = <&memc>;
  38                         clock-output-names = "xtal", "cpu", "bus",
  39                                              "50m", "125m", "150m",
  40 @@ -88,7 +90,7 @@
  41
  42                         clocks = <&sysc MT7621_CLK_I2C>;
  43                         clock-names = "i2c";
  44 -                       resets = <&rstctrl 16>;
  45 +                       resets = <&sysc MT7621_RST_I2C>;
  46                         reset-names = "i2c";
  47
  48                         #address-cells = <1>;
  49 @@ -161,7 +163,7 @@
  50                         clocks = <&sysc MT7621_CLK_SPI>;
  51                         clock-names = "spi";
  52
  53 -                       resets = <&rstctrl 18>;
  54 +                       resets = <&sysc MT7621_RST_SPI>;
  55                         reset-names = "spi";
  56
  57                         #address-cells = <1>;
  58 @@ -296,11 +298,6 @@
  59                 };
  60         };
  61
  62 -       rstctrl: rstctrl {
  63 -               compatible = "ralink,rt2880-reset";
  64 -               #reset-cells = <1>;
  65 -       };
  66 -
  67         sdhci: sdhci@1e130000 {
  68                 status = "disabled";
  69
  70 @@ -383,7 +380,7 @@
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74 -               resets = <&rstctrl 6 &rstctrl 23>;
  75 +               resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
  76                 reset-names = "fe", "eth";
  77
  78                 interrupt-parent = <&gic>;
  79 @@ -423,7 +420,7 @@
  80                                 #size-cells = <0>;
  81                                 reg = <0>;
  82                                 mediatek,mcm;
  83 -                               resets = <&rstctrl 2>;
  84 +                               resets = <&sysc MT7621_RST_MCM>;
  85                                 reset-names = "mcm";
  86                                 interrupt-controller;
  87                                 #interrupt-cells = <1>;
  88 @@ -516,7 +513,7 @@
  89                         #interrupt-cells = <1>;
  90                         interrupt-map-mask = <0 0 0 0>;
  91                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
  92 -                       resets = <&rstctrl 24>;
  93 +                       resets = <&sysc MT7621_RST_PCIE0>;
  94                         clocks = <&sysc MT7621_CLK_PCIE0>;
  95                         phys = <&pcie0_phy 1>;
  96                         phy-names = "pcie-phy0";
  97 @@ -531,7 +528,7 @@
  98                         #interrupt-cells = <1>;
  99                         interrupt-map-mask = <0 0 0 0>;
 100                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 101 -                       resets = <&rstctrl 25>;
 102 +                       resets = <&sysc MT7621_RST_PCIE1>;
 103                         clocks = <&sysc MT7621_CLK_PCIE1>;
 104                         phys = <&pcie0_phy 1>;
 105                         phy-names = "pcie-phy1";
 106 @@ -546,7 +543,7 @@
 107                         #interrupt-cells = <1>;
 108                         interrupt-map-mask = <0 0 0 0>;
 109                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 110 -                       resets = <&rstctrl 26>;
 111 +                       resets = <&sysc MT7621_RST_PCIE2>;
 112                         clocks = <&sysc MT7621_CLK_PCIE2>;
 113                         phys = <&pcie2_phy 0>;
 114                         phy-names = "pcie-phy2";