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1 From patchwork Wed Nov 2 00:58:01 2022
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
6 X-Patchwork-Id: 13027653
7 X-Patchwork-Delegate: kuba@kernel.org
8 Return-Path: <netdev-owner@kernel.org>
9 Date: Wed, 2 Nov 2022 00:58:01 +0000
10 From: Daniel Golle <daniel@makrotopia.org>
11 To: Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
12 Sean Wang <sean.wang@mediatek.com>,
13 Mark Lee <Mark-MC.Lee@mediatek.com>,
14 "David S. Miller" <davem@davemloft.net>,
15 Eric Dumazet <edumazet@google.com>,
16 Jakub Kicinski <kuba@kernel.org>,
17 Paolo Abeni <pabeni@redhat.com>,
18 Matthias Brugger <matthias.bgg@gmail.com>,
19 netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
20 linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
21 Subject: [PATCH v4] net: ethernet: mediatek: ppe: add support for flow
22 accounting
23 Message-ID: <Y2HAmYYPd77dz+K5@makrotopia.org>
24 MIME-Version: 1.0
25 Content-Disposition: inline
26 Precedence: bulk
27 List-ID: <netdev.vger.kernel.org>
28 X-Mailing-List: netdev@vger.kernel.org
29 X-Patchwork-Delegate: kuba@kernel.org
30
31 The PPE units found in MT7622 and newer support packet and byte
32 accounting of hw-offloaded flows. Add support for reading those
33 counters as found in MediaTek's SDK[1].
34
35 [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/bc6a6a375c800dc2b80e1a325a2c732d1737df92
36 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
37 ---
38 v4: declare function mtk_mib_entry_read as static
39 v3: don't bother to set 'false' values in any zero-initialized struct
40 use mtk_foe_entry_ib2
41 both changes were requested by Felix Fietkau
42
43 v2: fix wrong variable name in return value check spotted by Denis Kirjanov
44
45 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 +-
46 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
47 drivers/net/ethernet/mediatek/mtk_ppe.c | 110 +++++++++++++++++-
48 drivers/net/ethernet/mediatek/mtk_ppe.h | 23 +++-
49 .../net/ethernet/mediatek/mtk_ppe_debugfs.c | 9 +-
50 .../net/ethernet/mediatek/mtk_ppe_offload.c | 7 ++
51 drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 14 +++
52 7 files changed, 166 insertions(+), 5 deletions(-)
53
54 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
55 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
56 @@ -4637,8 +4637,8 @@ static int mtk_probe(struct platform_dev
57 for (i = 0; i < num_ppe; i++) {
58 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
59
60 - eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr,
61 - eth->soc->offload_version, i);
62 + eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
63 +
64 if (!eth->ppe[i]) {
65 err = -ENOMEM;
66 goto err_deinit_ppe;
67 @@ -4764,6 +4764,7 @@ static const struct mtk_soc_data mt7622_
68 .required_pctl = false,
69 .offload_version = 2,
70 .hash_offset = 2,
71 + .has_accounting = true,
72 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
73 .txrx = {
74 .txd_size = sizeof(struct mtk_tx_dma),
75 @@ -4801,6 +4802,7 @@ static const struct mtk_soc_data mt7629_
76 .hw_features = MTK_HW_FEATURES,
77 .required_clks = MT7629_CLKS_BITMAP,
78 .required_pctl = false,
79 + .has_accounting = true,
80 .txrx = {
81 .txd_size = sizeof(struct mtk_tx_dma),
82 .rxd_size = sizeof(struct mtk_rx_dma),
83 @@ -4821,6 +4823,7 @@ static const struct mtk_soc_data mt7981_
84 .offload_version = 2,
85 .hash_offset = 4,
86 .foe_entry_size = sizeof(struct mtk_foe_entry),
87 + .has_accounting = true,
88 .txrx = {
89 .txd_size = sizeof(struct mtk_tx_dma_v2),
90 .rxd_size = sizeof(struct mtk_rx_dma_v2),
91 @@ -4841,6 +4844,7 @@ static const struct mtk_soc_data mt7986_
92 .offload_version = 2,
93 .hash_offset = 4,
94 .foe_entry_size = sizeof(struct mtk_foe_entry),
95 + .has_accounting = true,
96 .txrx = {
97 .txd_size = sizeof(struct mtk_tx_dma_v2),
98 .rxd_size = sizeof(struct mtk_rx_dma_v2),
99 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
100 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
101 @@ -1008,6 +1008,8 @@ struct mtk_reg_map {
102 * the extra setup for those pins used by GMAC.
103 * @hash_offset Flow table hash offset.
104 * @foe_entry_size Foe table entry size.
105 + * @has_accounting Bool indicating support for accounting of
106 + * offloaded flows.
107 * @txd_size Tx DMA descriptor size.
108 * @rxd_size Rx DMA descriptor size.
109 * @rx_irq_done_mask Rx irq done register mask.
110 @@ -1025,6 +1027,7 @@ struct mtk_soc_data {
111 u8 hash_offset;
112 u16 foe_entry_size;
113 netdev_features_t hw_features;
114 + bool has_accounting;
115 struct {
116 u32 txd_size;
117 u32 rxd_size;
118 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
119 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
120 @@ -74,6 +74,48 @@ static int mtk_ppe_wait_busy(struct mtk_
121 return ret;
122 }
123
124 +static int mtk_ppe_mib_wait_busy(struct mtk_ppe *ppe)
125 +{
126 + int ret;
127 + u32 val;
128 +
129 + ret = readl_poll_timeout(ppe->base + MTK_PPE_MIB_SER_CR, val,
130 + !(val & MTK_PPE_MIB_SER_CR_ST),
131 + 20, MTK_PPE_WAIT_TIMEOUT_US);
132 +
133 + if (ret)
134 + dev_err(ppe->dev, "MIB table busy");
135 +
136 + return ret;
137 +}
138 +
139 +static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets)
140 +{
141 + u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high;
142 + u32 val, cnt_r0, cnt_r1, cnt_r2;
143 + int ret;
144 +
145 + val = FIELD_PREP(MTK_PPE_MIB_SER_CR_ADDR, index) | MTK_PPE_MIB_SER_CR_ST;
146 + ppe_w32(ppe, MTK_PPE_MIB_SER_CR, val);
147 +
148 + ret = mtk_ppe_mib_wait_busy(ppe);
149 + if (ret)
150 + return ret;
151 +
152 + cnt_r0 = readl(ppe->base + MTK_PPE_MIB_SER_R0);
153 + cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1);
154 + cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2);
155 +
156 + byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
157 + byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
158 + pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
159 + pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
160 + *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
161 + *packets = (pkt_cnt_high << 16) | pkt_cnt_low;
162 +
163 + return 0;
164 +}
165 +
166 static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
167 {
168 ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
169 @@ -465,6 +507,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
170 hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID);
171 dma_wmb();
172 mtk_ppe_cache_clear(ppe);
173 + if (ppe->accounting) {
174 + struct mtk_foe_accounting *acct;
175 +
176 + acct = ppe->acct_table + entry->hash * sizeof(*acct);
177 + acct->packets = 0;
178 + acct->bytes = 0;
179 + }
180 }
181 entry->hash = 0xffff;
182
183 @@ -572,6 +621,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
184 wmb();
185 hwe->ib1 = entry->ib1;
186
187 + if (ppe->accounting)
188 + *mtk_foe_entry_ib2(eth, hwe) |= MTK_FOE_IB2_MIB_CNT;
189 +
190 dma_wmb();
191
192 mtk_ppe_cache_clear(ppe);
193 @@ -763,11 +815,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
194 return mtk_ppe_wait_busy(ppe);
195 }
196
197 -struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
198 - int version, int index)
199 +struct mtk_foe_accounting *mtk_foe_entry_get_mib(struct mtk_ppe *ppe, u32 index,
200 + struct mtk_foe_accounting *diff)
201 +{
202 + struct mtk_foe_accounting *acct;
203 + int size = sizeof(struct mtk_foe_accounting);
204 + u64 bytes, packets;
205 +
206 + if (!ppe->accounting)
207 + return NULL;
208 +
209 + if (mtk_mib_entry_read(ppe, index, &bytes, &packets))
210 + return NULL;
211 +
212 + acct = ppe->acct_table + index * size;
213 +
214 + acct->bytes += bytes;
215 + acct->packets += packets;
216 +
217 + if (diff) {
218 + diff->bytes = bytes;
219 + diff->packets = packets;
220 + }
221 +
222 + return acct;
223 +}
224 +
225 +struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int index)
226 {
227 + bool accounting = eth->soc->has_accounting;
228 const struct mtk_soc_data *soc = eth->soc;
229 + struct mtk_foe_accounting *acct;
230 struct device *dev = eth->dev;
231 + struct mtk_mib_entry *mib;
232 struct mtk_ppe *ppe;
233 u32 foe_flow_size;
234 void *foe;
235 @@ -784,7 +864,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
236 ppe->base = base;
237 ppe->eth = eth;
238 ppe->dev = dev;
239 - ppe->version = version;
240 + ppe->version = eth->soc->offload_version;
241 + ppe->accounting = accounting;
242
243 foe = dmam_alloc_coherent(ppe->dev,
244 MTK_PPE_ENTRIES * soc->foe_entry_size,
245 @@ -800,6 +881,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
246 if (!ppe->foe_flow)
247 goto err_free_l2_flows;
248
249 + if (accounting) {
250 + mib = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*mib),
251 + &ppe->mib_phys, GFP_KERNEL);
252 + if (!mib)
253 + return NULL;
254 +
255 + ppe->mib_table = mib;
256 +
257 + acct = devm_kzalloc(dev, MTK_PPE_ENTRIES * sizeof(*acct),
258 + GFP_KERNEL);
259 +
260 + if (!acct)
261 + return NULL;
262 +
263 + ppe->acct_table = acct;
264 + }
265 +
266 mtk_ppe_debugfs_init(ppe, index);
267
268 return ppe;
269 @@ -929,6 +1027,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
270 ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
271 ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
272 }
273 +
274 + if (ppe->accounting && ppe->mib_phys) {
275 + ppe_w32(ppe, MTK_PPE_MIB_TB_BASE, ppe->mib_phys);
276 + ppe_m32(ppe, MTK_PPE_MIB_CFG, MTK_PPE_MIB_CFG_EN,
277 + MTK_PPE_MIB_CFG_EN);
278 + ppe_m32(ppe, MTK_PPE_MIB_CFG, MTK_PPE_MIB_CFG_RD_CLR,
279 + MTK_PPE_MIB_CFG_RD_CLR);
280 + ppe_m32(ppe, MTK_PPE_MIB_CACHE_CTL, MTK_PPE_MIB_CACHE_CTL_EN,
281 + MTK_PPE_MIB_CFG_RD_CLR);
282 + }
283 }
284
285 int mtk_ppe_stop(struct mtk_ppe *ppe)
286 --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
287 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
288 @@ -57,6 +57,7 @@ enum {
289 #define MTK_FOE_IB2_MULTICAST BIT(8)
290
291 #define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12)
292 +#define MTK_FOE_IB2_MIB_CNT BIT(15)
293 #define MTK_FOE_IB2_WDMA_DEVIDX BIT(16)
294 #define MTK_FOE_IB2_WDMA_WINFO BIT(17)
295
296 @@ -285,16 +286,34 @@ struct mtk_flow_entry {
297 unsigned long cookie;
298 };
299
300 +struct mtk_mib_entry {
301 + u32 byt_cnt_l;
302 + u16 byt_cnt_h;
303 + u32 pkt_cnt_l;
304 + u8 pkt_cnt_h;
305 + u8 _rsv0;
306 + u32 _rsv1;
307 +} __packed;
308 +
309 +struct mtk_foe_accounting {
310 + u64 bytes;
311 + u64 packets;
312 +};
313 +
314 struct mtk_ppe {
315 struct mtk_eth *eth;
316 struct device *dev;
317 void __iomem *base;
318 int version;
319 char dirname[5];
320 + bool accounting;
321
322 void *foe_table;
323 dma_addr_t foe_phys;
324
325 + struct mtk_mib_entry *mib_table;
326 + dma_addr_t mib_phys;
327 +
328 u16 foe_check_time[MTK_PPE_ENTRIES];
329 struct hlist_head *foe_flow;
330
331 @@ -303,8 +322,7 @@ struct mtk_ppe {
332 void *acct_table;
333 };
334
335 -struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
336 - int version, int index);
337 +struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int index);
338 void mtk_ppe_deinit(struct mtk_eth *eth);
339 void mtk_ppe_start(struct mtk_ppe *ppe);
340 int mtk_ppe_stop(struct mtk_ppe *ppe);
341 @@ -359,5 +377,7 @@ int mtk_foe_entry_commit(struct mtk_ppe
342 void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
343 int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
344 int mtk_ppe_debugfs_init(struct mtk_ppe *ppe, int index);
345 +struct mtk_foe_accounting *mtk_foe_entry_get_mib(struct mtk_ppe *ppe, u32 index,
346 + struct mtk_foe_accounting *diff);
347
348 #endif
349 --- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
350 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
351 @@ -82,6 +82,7 @@ mtk_ppe_debugfs_foe_show(struct seq_file
352 struct mtk_foe_entry *entry = mtk_foe_get_entry(ppe, i);
353 struct mtk_foe_mac_info *l2;
354 struct mtk_flow_addr_info ai = {};
355 + struct mtk_foe_accounting *acct;
356 unsigned char h_source[ETH_ALEN];
357 unsigned char h_dest[ETH_ALEN];
358 int type, state;
359 @@ -95,6 +96,8 @@ mtk_ppe_debugfs_foe_show(struct seq_file
360 if (bind && state != MTK_FOE_STATE_BIND)
361 continue;
362
363 + acct = mtk_foe_entry_get_mib(ppe, i, NULL);
364 +
365 type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
366 seq_printf(m, "%05x %s %7s", i,
367 mtk_foe_entry_state_str(state),
368 @@ -153,9 +156,11 @@ mtk_ppe_debugfs_foe_show(struct seq_file
369 *((__be16 *)&h_dest[4]) = htons(l2->dest_mac_lo);
370
371 seq_printf(m, " eth=%pM->%pM etype=%04x"
372 - " vlan=%d,%d ib1=%08x ib2=%08x\n",
373 + " vlan=%d,%d ib1=%08x ib2=%08x"
374 + " packets=%llu bytes=%llu\n",
375 h_source, h_dest, ntohs(l2->etype),
376 - l2->vlan1, l2->vlan2, entry->ib1, ib2);
377 + l2->vlan1, l2->vlan2, entry->ib1, ib2,
378 + acct ? acct->packets : 0, acct ? acct->bytes : 0);
379 }
380
381 return 0;
382 --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
383 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
384 @@ -497,6 +497,7 @@ static int
385 mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f)
386 {
387 struct mtk_flow_entry *entry;
388 + struct mtk_foe_accounting diff;
389 u32 idle;
390
391 entry = rhashtable_lookup(&eth->flow_table, &f->cookie,
392 @@ -507,6 +508,13 @@ mtk_flow_offload_stats(struct mtk_eth *e
393 idle = mtk_foe_entry_idle_time(eth->ppe[entry->ppe_index], entry);
394 f->stats.lastused = jiffies - idle * HZ;
395
396 + if (entry->hash != 0xFFFF &&
397 + mtk_foe_entry_get_mib(eth->ppe[entry->ppe_index], entry->hash,
398 + &diff)) {
399 + f->stats.pkts += diff.packets;
400 + f->stats.bytes += diff.bytes;
401 + }
402 +
403 return 0;
404 }
405
406 --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
407 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
408 @@ -149,6 +149,20 @@ enum {
409
410 #define MTK_PPE_MIB_TB_BASE 0x338
411
412 +#define MTK_PPE_MIB_SER_CR 0x33C
413 +#define MTK_PPE_MIB_SER_CR_ST BIT(16)
414 +#define MTK_PPE_MIB_SER_CR_ADDR GENMASK(13, 0)
415 +
416 +#define MTK_PPE_MIB_SER_R0 0x340
417 +#define MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW GENMASK(31, 0)
418 +
419 +#define MTK_PPE_MIB_SER_R1 0x344
420 +#define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW GENMASK(31, 16)
421 +#define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH GENMASK(15, 0)
422 +
423 +#define MTK_PPE_MIB_SER_R2 0x348
424 +#define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0)
425 +
426 #define MTK_PPE_MIB_CACHE_CTL 0x350
427 #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
428 #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)
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