git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 1414d30660d201f515a9d877571ceea9ca190b6a Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
   3 Date: Mon, 29 May 2023 10:02:43 +0200
   4 Subject: [PATCH 3/6] net: dsa: mv88e6xxx: add field to specify internal phys
   5  layout
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 mv88e6xxx currently assumes that switch equipped with internal phys have
  11 those phys mapped contiguously starting from port 0 (see
  12 mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
  13 NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
  14 integrated PHYs available on ports 1 to 8
  15 To properly support this offset, add a new field to allow specifying an
  16 internal PHYs layout. If field is not set, default layout is assumed (start
  17 at port 0)
  18
  19 Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
  20 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  21 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  22 ---
  23  drivers/net/dsa/mv88e6xxx/chip.c    | 4 +++-
  24  drivers/net/dsa/mv88e6xxx/chip.h    | 5 +++++
  25  drivers/net/dsa/mv88e6xxx/global2.c | 5 ++++-
  26  3 files changed, 12 insertions(+), 2 deletions(-)
  27
  28 --- a/drivers/net/dsa/mv88e6xxx/chip.c
  29 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
  30 @@ -472,7 +472,9 @@ restore_link:
  31
  32  static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
  33  {
  34 -       return port < chip->info->num_internal_phys;
  35 +       return port >= chip->info->internal_phys_offset &&
  36 +               port < chip->info->num_internal_phys +
  37 +                       chip->info->internal_phys_offset;
  38  }
  39
  40  static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
  41 --- a/drivers/net/dsa/mv88e6xxx/chip.h
  42 +++ b/drivers/net/dsa/mv88e6xxx/chip.h
  43 @@ -167,6 +167,11 @@ struct mv88e6xxx_info {
  44
  45         /* Supports PTP */
  46         bool ptp_support;
  47 +
  48 +       /* Internal PHY start index. 0 means that internal PHYs range starts at
  49 +        * port 0, 1 means internal PHYs range starts at port 1, etc
  50 +        */
  51 +       unsigned int internal_phys_offset;
  52  };
  53
  54  struct mv88e6xxx_atu_entry {
  55 --- a/drivers/net/dsa/mv88e6xxx/global2.c
  56 +++ b/drivers/net/dsa/mv88e6xxx/global2.c
  57 @@ -1185,8 +1185,11 @@ int mv88e6xxx_g2_irq_mdio_setup(struct m
  58                                 struct mii_bus *bus)
  59  {
  60         int phy, irq, err, err_phy;
  61 +       int phy_start = chip->info->internal_phys_offset;
  62 +       int phy_end = chip->info->internal_phys_offset +
  63 +                     chip->info->num_internal_phys;
  64
  65 -       for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
  66 +       for (phy = phy_start; phy < phy_end; phy++) {
  67                 irq = irq_find_mapping(chip->g2_irq.domain, phy);
  68                 if (irq < 0) {
  69                         err = irq;