git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 081c9c0265c91b8333165aa6230c20bcbc6f7cbf Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Thu, 10 Oct 2024 14:07:16 +0100
   4 Subject: [PATCH 3/5] net: phy: realtek: read duplex and gbit master from PHYSR
   5  register
   6
   7 The PHYSR MMD register is present and defined equally for all RTL82xx
   8 Ethernet PHYs.
   9 Read duplex and Gbit master bits from rtlgen_decode_speed() and rename
  10 it to rtlgen_decode_physr().
  11
  12 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  13 Link: https://patch.msgid.link/b9a76341da851a18c985bc4774fa295babec79bb.1728565530.git.daniel@makrotopia.org
  14 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  15 ---
  16  drivers/net/phy/realtek.c | 41 +++++++++++++++++++++++++++++++--------
  17  1 file changed, 33 insertions(+), 8 deletions(-)
  18
  19 --- a/drivers/net/phy/realtek.c
  20 +++ b/drivers/net/phy/realtek.c
  21 @@ -80,15 +80,18 @@
  22
  23  #define RTL822X_VND2_GANLPAR                           0xa414
  24
  25 -#define RTL822X_VND2_PHYSR                             0xa434
  26 -
  27  #define RTL8366RB_POWER_SAVE                   0x15
  28  #define RTL8366RB_POWER_SAVE_ON                        BIT(12)
  29
  30  #define RTL9000A_GINMR                         0x14
  31  #define RTL9000A_GINMR_LINK_STATUS             BIT(4)
  32
  33 -#define RTLGEN_SPEED_MASK                      0x0630
  34 +#define RTL_VND2_PHYSR                         0xa434
  35 +#define RTL_VND2_PHYSR_DUPLEX                  BIT(3)
  36 +#define RTL_VND2_PHYSR_SPEEDL                  GENMASK(5, 4)
  37 +#define RTL_VND2_PHYSR_SPEEDH                  GENMASK(10, 9)
  38 +#define RTL_VND2_PHYSR_MASTER                  BIT(11)
  39 +#define RTL_VND2_PHYSR_SPEED_MASK              (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
  40
  41  #define RTL_GENERIC_PHYID                      0x001cc800
  42  #define RTL_8211FVD_PHYID                      0x001cc878
  43 @@ -660,9 +663,18 @@ static int rtl8366rb_config_init(struct
  44  }
  45
  46  /* get actual speed to cover the downshift case */
  47 -static void rtlgen_decode_speed(struct phy_device *phydev, int val)
  48 +static void rtlgen_decode_physr(struct phy_device *phydev, int val)
  49  {
  50 -       switch (val & RTLGEN_SPEED_MASK) {
  51 +       /* bit 3
  52 +        * 0: Half Duplex
  53 +        * 1: Full Duplex
  54 +        */
  55 +       if (val & RTL_VND2_PHYSR_DUPLEX)
  56 +               phydev->duplex = DUPLEX_FULL;
  57 +       else
  58 +               phydev->duplex = DUPLEX_HALF;
  59 +
  60 +       switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
  61         case 0x0000:
  62                 phydev->speed = SPEED_10;
  63                 break;
  64 @@ -684,6 +696,19 @@ static void rtlgen_decode_speed(struct p
  65         default:
  66                 break;
  67         }
  68 +
  69 +       /* bit 11
  70 +        * 0: Slave Mode
  71 +        * 1: Master Mode
  72 +        */
  73 +       if (phydev->speed >= 1000) {
  74 +               if (val & RTL_VND2_PHYSR_MASTER)
  75 +                       phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
  76 +               else
  77 +                       phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
  78 +       } else {
  79 +               phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
  80 +       }
  81  }
  82
  83  static int rtlgen_read_status(struct phy_device *phydev)
  84 @@ -701,7 +726,7 @@ static int rtlgen_read_status(struct phy
  85         if (val < 0)
  86                 return val;
  87
  88 -       rtlgen_decode_speed(phydev, val);
  89 +       rtlgen_decode_physr(phydev, val);
  90
  91         return 0;
  92  }
  93 @@ -1007,11 +1032,11 @@ static int rtl822x_c45_read_status(struc
  94                 return 0;
  95
  96         /* Read actual speed from vendor register. */
  97 -       val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR);
  98 +       val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
  99         if (val < 0)
 100                 return val;
 101
 102 -       rtlgen_decode_speed(phydev, val);
 103 +       rtlgen_decode_physr(phydev, val);
 104
 105         return 0;
 106  }