git.openwrt.org Git - openwrt/staging/zorun.git/blob

   1 From fcdefccac976ee51dd6071832b842d8fb41c479c Mon Sep 17 00:00:00 2001
   2 From: Andy Gospodarek <gospo@broadcom.com>
   3 Date: Mon, 31 Oct 2016 13:32:03 -0400
   4 Subject: [PATCH] bgmac: stop clearing DMA receive control register right after
   5  it is set
   6
   7 Current bgmac code initializes some DMA settings in the receive control
   8 register for some hardware and then immediately clears those settings.
   9 Not clearing those settings results in ~420Mbps *improvement* in
  10 throughput; this system can now receive frames at line-rate on Broadcom
  11 5871x hardware compared to ~520Mbps today.  I also tested a few other
  12 values but found there to be no discernible difference in CPU
  13 utilization even if burst size and prefetching values are different.
  14
  15 On the hardware tested there was no need to keep the code that cleared
  16 all but bits 16-17, but since there is a wide variety of hardware that
  17 used this driver (I did not look at all hardware docs for hardware using
  18 this IP block), I find it wise to move this call up and clear bits just
  19 after reading the default value from the hardware rather than completely
  20 removing it.
  21
  22 This is a good candidate for -stable >=3.14 since that is when the code
  23 that was supposed to improve performance (but did not) was introduced.
  24
  25 Signed-off-by: Andy Gospodarek <gospo@broadcom.com>
  26 Fixes: 56ceecde1f29 ("bgmac: initialize the DMA controller of core...")
  27 Cc: Hauke Mehrtens <hauke@hauke-m.de>
  28 Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
  29 Signed-off-by: David S. Miller <davem@davemloft.net>
  30 ---
  31  drivers/net/ethernet/broadcom/bgmac.c | 5 ++++-
  32  1 file changed, 4 insertions(+), 1 deletion(-)
  33
  34 --- a/drivers/net/ethernet/broadcom/bgmac.c
  35 +++ b/drivers/net/ethernet/broadcom/bgmac.c
  36 @@ -307,6 +307,10 @@ static void bgmac_dma_rx_enable(struct b
  37         u32 ctl;
  38
  39         ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
  40 +
  41 +       /* preserve ONLY bits 16-17 from current hardware value */
  42 +       ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
  43 +
  44         if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
  45                 ctl &= ~BGMAC_DMA_RX_BL_MASK;
  46                 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
  47 @@ -317,7 +321,6 @@ static void bgmac_dma_rx_enable(struct b
  48                 ctl &= ~BGMAC_DMA_RX_PT_MASK;
  49                 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
  50         }
  51 -       ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
  52         ctl |= BGMAC_DMA_RX_ENABLE;
  53         ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
  54         ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;