e07e120ed098a398753149253b7f40aac4f83277
[openwrt/staging/blocktrron.git] /
1 From 43c5632ea7b6b4dfc8f7d411003bf0cf030b4263 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Fri, 17 Feb 2023 15:07:29 +0100
4 Subject: [PATCH 0587/1085] drm/vc4: hvs: Use switch statement to simplify
5 vc4_hvs_get_fifo_from_output
6
7 Since we'll support BCM2712 soon, let's move the logic behind
8 vc4_hvs_get_fifo_from_output() to a switch to extend it more easily.
9
10 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
11 ---
12 drivers/gpu/drm/vc4/vc4_hvs.c | 80 +++++++++++++++++++----------------
13 1 file changed, 43 insertions(+), 37 deletions(-)
14
15 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
16 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
17 @@ -620,57 +620,63 @@ int vc4_hvs_get_fifo_from_output(struct
18 u32 reg;
19 int ret;
20
21 - if (vc4->gen == VC4_GEN_4)
22 + switch (vc4->gen) {
23 + case VC4_GEN_4:
24 return output;
25
26 - /*
27 - * NOTE: We should probably use drm_dev_enter()/drm_dev_exit()
28 - * here, but this function is only used during the DRM device
29 - * initialization, so we should be fine.
30 - */
31 -
32 - switch (output) {
33 - case 0:
34 - return 0;
35 -
36 - case 1:
37 - return 1;
38 -
39 - case 2:
40 - reg = HVS_READ(SCALER_DISPECTRL);
41 - ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
42 - if (ret == 0)
43 - return 2;
44 -
45 - return 0;
46 -
47 - case 3:
48 - reg = HVS_READ(SCALER_DISPCTRL);
49 - ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
50 - if (ret == 3)
51 - return -EPIPE;
52 -
53 - return ret;
54 -
55 - case 4:
56 - reg = HVS_READ(SCALER_DISPEOLN);
57 - ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
58 - if (ret == 3)
59 - return -EPIPE;
60 + case VC4_GEN_5:
61 + /*
62 + * NOTE: We should probably use
63 + * drm_dev_enter()/drm_dev_exit() here, but this
64 + * function is only used during the DRM device
65 + * initialization, so we should be fine.
66 + */
67 +
68 + switch (output) {
69 + case 0:
70 + return 0;
71 +
72 + case 1:
73 + return 1;
74 +
75 + case 2:
76 + reg = HVS_READ(SCALER_DISPECTRL);
77 + ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
78 + if (ret == 0)
79 + return 2;
80 +
81 + return 0;
82 +
83 + case 3:
84 + reg = HVS_READ(SCALER_DISPCTRL);
85 + ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
86 + if (ret == 3)
87 + return -EPIPE;
88 +
89 + return ret;
90 +
91 + case 4:
92 + reg = HVS_READ(SCALER_DISPEOLN);
93 + ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
94 + if (ret == 3)
95 + return -EPIPE;
96 +
97 + return ret;
98 +
99 + case 5:
100 + reg = HVS_READ(SCALER_DISPDITHER);
101 + ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
102 + if (ret == 3)
103 + return -EPIPE;
104
105 - return ret;
106 + return ret;
107
108 - case 5:
109 - reg = HVS_READ(SCALER_DISPDITHER);
110 - ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
111 - if (ret == 3)
112 + default:
113 return -EPIPE;
114 -
115 - return ret;
116 -
117 - default:
118 - return -EPIPE;
119 + }
120 }
121 +
122 + return -EPIPE;
123 }
124
125 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,