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1 From 859df5cf6ff07a9c930be4681284346aa73dd1fb Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
3 Date: Fri, 1 Mar 2024 12:43:01 +0200
4 Subject: [PATCH 23/30] net: dsa: mt7530: get rid of
5 priv->info->cpu_port_config()
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 priv->info->cpu_port_config() is used for MT7531 and the switch on the
11 MT7988 SoC. It sets up the ports described as a CPU port earlier than the
12 phylink code path would do.
13
14 This function is useless as:
15 - Configuring the MACs can be done from the phylink_mac_config code path
16 instead.
17 - All the link configuration it does on the CPU ports are later undone with
18 the port_enable, phylink_mac_config, and then phylink_mac_link_up code
19 path [1].
20
21 priv->p5_interface and priv->p6_interface were being used to prevent
22 configuring the MACs from the phylink_mac_config code path. Remove them now
23 that they hold no purpose.
24
25 Remove priv->info->cpu_port_config(). On mt753x_phylink_mac_config, switch
26 to if statements to simplify the code.
27
28 Remove the overwriting of the speed and duplex interfaces for certain
29 interface modes. Phylink already provides the speed and duplex variables
30 with proper values. Phylink already sets the max speed of TRGMII to
31 SPEED_1000. Add SPEED_2500 for PHY_INTERFACE_MODE_2500BASEX to where the
32 speed and EEE bits are set instead.
33
34 On the switch on the MT7988 SoC, PHY_INTERFACE_MODE_INTERNAL is being used
35 to describe the interface mode of the 10G MAC, which is of port 6. On
36 mt7988_cpu_port_config() PMCR_FORCE_SPEED_1000 was set via the
37 PMCR_CPU_PORT_SETTING() mask. Add SPEED_10000 case to where the speed bits
38 are set to cover this. No need to add it to where the EEE bits are set as
39 the "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
40 v0.1" document shows that these bits don't exist on the MT7530_PMCR_P(6)
41 register.
42
43 Remove the definition of PMCR_CPU_PORT_SETTING() now that it holds no
44 purpose.
45
46 Change mt753x_cpu_port_enable() to void now that there're no error cases
47 left.
48
49 Link: https://lore.kernel.org/netdev/ZHy2jQLesdYFMQtO@shell.armlinux.org.uk/ [1]
50 Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
51 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
52 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
53 ---
54 drivers/net/dsa/mt7530.c | 114 +++------------------------------------
55 drivers/net/dsa/mt7530.h | 11 ----
56 2 files changed, 7 insertions(+), 118 deletions(-)
57
58 --- a/drivers/net/dsa/mt7530.c
59 +++ b/drivers/net/dsa/mt7530.c
60 @@ -1002,18 +1002,10 @@ mt753x_trap_frames(struct mt7530_priv *p
61 MT753X_BPDU_CPU_ONLY);
62 }
63
64 -static int
65 +static void
66 mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
67 {
68 struct mt7530_priv *priv = ds->priv;
69 - int ret;
70 -
71 - /* Setup max capability of CPU port at first */
72 - if (priv->info->cpu_port_config) {
73 - ret = priv->info->cpu_port_config(ds, port);
74 - if (ret)
75 - return ret;
76 - }
77
78 /* Enable Mediatek header mode on the cpu port */
79 mt7530_write(priv, MT7530_PVC_P(port),
80 @@ -1039,8 +1031,6 @@ mt753x_cpu_port_enable(struct dsa_switch
81 /* Set to fallback mode for independent VLAN learning */
82 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
83 MT7530_PORT_FALLBACK_MODE);
84 -
85 - return 0;
86 }
87
88 static int
89 @@ -2297,8 +2287,6 @@ mt7530_setup(struct dsa_switch *ds)
90 val |= MHWTRAP_MANUAL;
91 mt7530_write(priv, MT7530_MHWTRAP, val);
92
93 - priv->p6_interface = PHY_INTERFACE_MODE_NA;
94 -
95 mt753x_trap_frames(priv);
96
97 /* Enable and reset MIB counters */
98 @@ -2313,9 +2301,7 @@ mt7530_setup(struct dsa_switch *ds)
99 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
100
101 if (dsa_is_cpu_port(ds, i)) {
102 - ret = mt753x_cpu_port_enable(ds, i);
103 - if (ret)
104 - return ret;
105 + mt753x_cpu_port_enable(ds, i);
106 } else {
107 mt7530_port_disable(ds, i);
108
109 @@ -2419,9 +2405,7 @@ mt7531_setup_common(struct dsa_switch *d
110 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
111
112 if (dsa_is_cpu_port(ds, i)) {
113 - ret = mt753x_cpu_port_enable(ds, i);
114 - if (ret)
115 - return ret;
116 + mt753x_cpu_port_enable(ds, i);
117 } else {
118 mt7530_port_disable(ds, i);
119
120 @@ -2510,10 +2494,6 @@ mt7531_setup(struct dsa_switch *ds)
121 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
122 MT7531_GPIO0_INTERRUPT);
123
124 - /* Let phylink decide the interface later. */
125 - priv->p5_interface = PHY_INTERFACE_MODE_NA;
126 - priv->p6_interface = PHY_INTERFACE_MODE_NA;
127 -
128 /* Enable PHY core PLL, since phy_device has not yet been created
129 * provided for phy_[read,write]_mmd_indirect is called, we provide
130 * our own mt7531_ind_mmd_phy_[read,write] to complete this
131 @@ -2725,26 +2705,9 @@ mt753x_phylink_mac_config(struct dsa_swi
132 struct mt7530_priv *priv = ds->priv;
133 u32 mcr_cur, mcr_new;
134
135 - switch (port) {
136 - case 5:
137 - if (priv->p5_interface == state->interface)
138 - break;
139 -
140 + if (port == 5 || port == 6)
141 mt753x_mac_config(ds, port, mode, state);
142
143 - if (priv->p5_intf_sel != P5_DISABLED)
144 - priv->p5_interface = state->interface;
145 - break;
146 - case 6:
147 - if (priv->p6_interface == state->interface)
148 - break;
149 -
150 - mt753x_mac_config(ds, port, mode, state);
151 -
152 - priv->p6_interface = state->interface;
153 - break;
154 - }
155 -
156 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
157 mcr_new = mcr_cur;
158 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
159 @@ -2780,17 +2743,10 @@ static void mt753x_phylink_mac_link_up(s
160
161 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
162
163 - /* MT753x MAC works in 1G full duplex mode for all up-clocked
164 - * variants.
165 - */
166 - if (interface == PHY_INTERFACE_MODE_TRGMII ||
167 - (phy_interface_mode_is_8023z(interface))) {
168 - speed = SPEED_1000;
169 - duplex = DUPLEX_FULL;
170 - }
171 -
172 switch (speed) {
173 case SPEED_1000:
174 + case SPEED_2500:
175 + case SPEED_10000:
176 mcr |= PMCR_FORCE_SPEED_1000;
177 break;
178 case SPEED_100:
179 @@ -2808,6 +2764,7 @@ static void mt753x_phylink_mac_link_up(s
180 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
181 switch (speed) {
182 case SPEED_1000:
183 + case SPEED_2500:
184 mcr |= PMCR_FORCE_EEE1G;
185 break;
186 case SPEED_100:
187 @@ -2819,61 +2776,6 @@ static void mt753x_phylink_mac_link_up(s
188 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
189 }
190
191 -static int
192 -mt7531_cpu_port_config(struct dsa_switch *ds, int port)
193 -{
194 - struct mt7530_priv *priv = ds->priv;
195 - phy_interface_t interface;
196 - int speed;
197 -
198 - switch (port) {
199 - case 5:
200 - if (!priv->p5_sgmii)
201 - interface = PHY_INTERFACE_MODE_RGMII;
202 - else
203 - interface = PHY_INTERFACE_MODE_2500BASEX;
204 -
205 - priv->p5_interface = interface;
206 - break;
207 - case 6:
208 - interface = PHY_INTERFACE_MODE_2500BASEX;
209 -
210 - priv->p6_interface = interface;
211 - break;
212 - default:
213 - return -EINVAL;
214 - }
215 -
216 - if (interface == PHY_INTERFACE_MODE_2500BASEX)
217 - speed = SPEED_2500;
218 - else
219 - speed = SPEED_1000;
220 -
221 - mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
222 -
223 - mt7530_write(priv, MT7530_PMCR_P(port),
224 - PMCR_CPU_PORT_SETTING(priv->id));
225 - mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
226 - speed, DUPLEX_FULL, true, true);
227 -
228 - return 0;
229 -}
230 -
231 -static int
232 -mt7988_cpu_port_config(struct dsa_switch *ds, int port)
233 -{
234 - struct mt7530_priv *priv = ds->priv;
235 -
236 - mt7530_write(priv, MT7530_PMCR_P(port),
237 - PMCR_CPU_PORT_SETTING(priv->id));
238 -
239 - mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
240 - PHY_INTERFACE_MODE_INTERNAL, NULL,
241 - SPEED_10000, DUPLEX_FULL, true, true);
242 -
243 - return 0;
244 -}
245 -
246 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
247 struct phylink_config *config)
248 {
249 @@ -3132,7 +3034,6 @@ const struct mt753x_info mt753x_table[]
250 .phy_write_c22 = mt7531_ind_c22_phy_write,
251 .phy_read_c45 = mt7531_ind_c45_phy_read,
252 .phy_write_c45 = mt7531_ind_c45_phy_write,
253 - .cpu_port_config = mt7531_cpu_port_config,
254 .mac_port_get_caps = mt7531_mac_port_get_caps,
255 .mac_port_config = mt7531_mac_config,
256 },
257 @@ -3144,7 +3045,6 @@ const struct mt753x_info mt753x_table[]
258 .phy_write_c22 = mt7531_ind_c22_phy_write,
259 .phy_read_c45 = mt7531_ind_c45_phy_read,
260 .phy_write_c45 = mt7531_ind_c45_phy_write,
261 - .cpu_port_config = mt7988_cpu_port_config,
262 .mac_port_get_caps = mt7988_mac_port_get_caps,
263 },
264 };
265 --- a/drivers/net/dsa/mt7530.h
266 +++ b/drivers/net/dsa/mt7530.h
267 @@ -331,13 +331,6 @@ enum mt7530_vlan_port_acc_frm {
268 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
269 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
270 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
271 -#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
272 - PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
273 - PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
274 - PMCR_TX_EN | PMCR_RX_EN | \
275 - PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
276 - PMCR_FORCE_SPEED_1000 | \
277 - PMCR_FORCE_FDX | PMCR_FORCE_LNK)
278
279 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
280 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
281 @@ -744,7 +737,6 @@ struct mt753x_info {
282 int regnum);
283 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
284 int regnum, u16 val);
285 - int (*cpu_port_config)(struct dsa_switch *ds, int port);
286 void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
287 struct phylink_config *config);
288 void (*mac_port_validate)(struct dsa_switch *ds, int port,
289 @@ -770,7 +762,6 @@ struct mt753x_info {
290 * @ports: Holding the state among ports
291 * @reg_mutex: The lock for protecting among process accessing
292 * registers
293 - * @p6_interface Holding the current port 6 interface
294 * @p5_intf_sel: Holding the current port 5 interface select
295 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
296 * has got SGMII
297 @@ -792,8 +783,6 @@ struct mt7530_priv {
298 const struct mt753x_info *info;
299 unsigned int id;
300 bool mcm;
301 - phy_interface_t p6_interface;
302 - phy_interface_t p5_interface;
303 enum p5_interface_select p5_intf_sel;
304 bool p5_sgmii;
305 u8 mirror_rx;
Staging tree of Matthias Schiffer