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1 From dcef754861ddd47e88f722abefc768410f1a17d1 Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
3 Date: Thu, 16 Feb 2023 00:30:01 +0200
4 Subject: [PATCH] media: i2c: imx290: Add support for 74.25MHz external
5 clock
6
7 Should be upstream commit b8b86dfe1aee
8
9 The sensor supports either a 37.125 or 74.25MHz external, but
10 the driver only supported 37.125MHz.
11
12 Add the relevant register configuration for either clock
13 frequency option.
14
15 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
16 Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
17 Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
18 Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
20 ---
21 drivers/media/i2c/imx290.c | 132 ++++++++++++++++++++++++++++++++-----
22 1 file changed, 116 insertions(+), 16 deletions(-)
23
24 --- a/drivers/media/i2c/imx290.c
25 +++ b/drivers/media/i2c/imx290.c
26 @@ -105,6 +105,7 @@
27 #define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452)
28 #define IMX290_TLPX IMX290_REG_16BIT(0x3454)
29 #define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472)
30 +#define IMX290_INCKSEL7 IMX290_REG_8BIT(0x3480)
31
32 #define IMX290_PGCTRL_REGEN BIT(0)
33 #define IMX290_PGCTRL_THRU BIT(1)
34 @@ -181,11 +182,29 @@ struct imx290_model_info {
35 enum imx290_colour_variant colour_variant;
36 };
37
38 +enum imx290_clk_freq {
39 + IMX290_CLK_37_125,
40 + IMX290_CLK_74_25,
41 + IMX290_NUM_CLK
42 +};
43 +
44 struct imx290_regval {
45 u32 reg;
46 u32 val;
47 };
48
49 +/*
50 + * Clock configuration for registers INCKSEL1 to INCKSEL6.
51 + */
52 +struct imx290_clk_cfg {
53 + u8 incksel1;
54 + u8 incksel2;
55 + u8 incksel3;
56 + u8 incksel4;
57 + u8 incksel5;
58 + u8 incksel6;
59 +};
60 +
61 struct imx290_mode {
62 u32 width;
63 u32 height;
64 @@ -195,6 +214,8 @@ struct imx290_mode {
65
66 const struct imx290_regval *data;
67 u32 data_size;
68 +
69 + const struct imx290_clk_cfg *clk_cfg;
70 };
71
72 struct imx290_csi_cfg {
73 @@ -213,6 +234,7 @@ struct imx290 {
74 struct device *dev;
75 struct clk *xclk;
76 struct regmap *regmap;
77 + enum imx290_clk_freq xclk_idx;
78 u8 nlanes;
79 const struct imx290_model_info *model;
80
81 @@ -241,7 +263,6 @@ static inline struct imx290 *to_imx290(s
82 */
83
84 static const struct imx290_regval imx290_global_init_settings[] = {
85 - { IMX290_EXTCK_FREQ, 0x2520 },
86 { IMX290_WINWV_OB, 12 },
87 { IMX290_WINPH, 0 },
88 { IMX290_WINPV, 0 },
89 @@ -291,7 +312,18 @@ static const struct imx290_regval imx290
90 { IMX290_REG_8BIT(0x33b0), 0x50 },
91 { IMX290_REG_8BIT(0x33b2), 0x1a },
92 { IMX290_REG_8BIT(0x33b3), 0x04 },
93 - { IMX290_REG_8BIT(0x3480), 0x49 },
94 +};
95 +
96 +#define IMX290_NUM_CLK_REGS 2
97 +static const struct imx290_regval xclk_regs[][IMX290_NUM_CLK_REGS] = {
98 + [IMX290_CLK_37_125] = {
99 + { IMX290_EXTCK_FREQ, (37125 * 256) / 1000 },
100 + { IMX290_INCKSEL7, 0x49 },
101 + },
102 + [IMX290_CLK_74_25] = {
103 + { IMX290_EXTCK_FREQ, (74250 * 256) / 1000 },
104 + { IMX290_INCKSEL7, 0x92 },
105 + },
106 };
107
108 static const struct imx290_regval imx290_1080p_settings[] = {
109 @@ -301,12 +333,6 @@ static const struct imx290_regval imx290
110 { IMX290_OPB_SIZE_V, 10 },
111 { IMX290_X_OUT_SIZE, 1920 },
112 { IMX290_Y_OUT_SIZE, 1080 },
113 - { IMX290_INCKSEL1, 0x18 },
114 - { IMX290_INCKSEL2, 0x03 },
115 - { IMX290_INCKSEL3, 0x20 },
116 - { IMX290_INCKSEL4, 0x01 },
117 - { IMX290_INCKSEL5, 0x1a },
118 - { IMX290_INCKSEL6, 0x1a },
119 };
120
121 static const struct imx290_regval imx290_720p_settings[] = {
122 @@ -316,12 +342,6 @@ static const struct imx290_regval imx290
123 { IMX290_OPB_SIZE_V, 4 },
124 { IMX290_X_OUT_SIZE, 1280 },
125 { IMX290_Y_OUT_SIZE, 720 },
126 - { IMX290_INCKSEL1, 0x20 },
127 - { IMX290_INCKSEL2, 0x00 },
128 - { IMX290_INCKSEL3, 0x20 },
129 - { IMX290_INCKSEL4, 0x01 },
130 - { IMX290_INCKSEL5, 0x1a },
131 - { IMX290_INCKSEL6, 0x1a },
132 };
133
134 static const struct imx290_regval imx290_10bit_settings[] = {
135 @@ -427,6 +447,48 @@ static inline int imx290_link_freqs_num(
136 return ARRAY_SIZE(imx290_link_freq_4lanes);
137 }
138
139 +static const struct imx290_clk_cfg imx290_1080p_clock_config[] = {
140 + [IMX290_CLK_37_125] = {
141 + /* 37.125MHz clock config */
142 + .incksel1 = 0x18,
143 + .incksel2 = 0x03,
144 + .incksel3 = 0x20,
145 + .incksel4 = 0x01,
146 + .incksel5 = 0x1a,
147 + .incksel6 = 0x1a,
148 + },
149 + [IMX290_CLK_74_25] = {
150 + /* 74.25MHz clock config */
151 + .incksel1 = 0x0c,
152 + .incksel2 = 0x03,
153 + .incksel3 = 0x10,
154 + .incksel4 = 0x01,
155 + .incksel5 = 0x1b,
156 + .incksel6 = 0x1b,
157 + },
158 +};
159 +
160 +static const struct imx290_clk_cfg imx290_720p_clock_config[] = {
161 + [IMX290_CLK_37_125] = {
162 + /* 37.125MHz clock config */
163 + .incksel1 = 0x20,
164 + .incksel2 = 0x00,
165 + .incksel3 = 0x20,
166 + .incksel4 = 0x01,
167 + .incksel5 = 0x1a,
168 + .incksel6 = 0x1a,
169 + },
170 + [IMX290_CLK_74_25] = {
171 + /* 74.25MHz clock config */
172 + .incksel1 = 0x10,
173 + .incksel2 = 0x00,
174 + .incksel3 = 0x10,
175 + .incksel4 = 0x01,
176 + .incksel5 = 0x1b,
177 + .incksel6 = 0x1b,
178 + },
179 +};
180 +
181 /* Mode configs */
182 static const struct imx290_mode imx290_modes_2lanes[] = {
183 {
184 @@ -437,6 +499,7 @@ static const struct imx290_mode imx290_m
185 .link_freq_index = FREQ_INDEX_1080P,
186 .data = imx290_1080p_settings,
187 .data_size = ARRAY_SIZE(imx290_1080p_settings),
188 + .clk_cfg = imx290_1080p_clock_config,
189 },
190 {
191 .width = 1280,
192 @@ -446,6 +509,7 @@ static const struct imx290_mode imx290_m
193 .link_freq_index = FREQ_INDEX_720P,
194 .data = imx290_720p_settings,
195 .data_size = ARRAY_SIZE(imx290_720p_settings),
196 + .clk_cfg = imx290_720p_clock_config,
197 },
198 };
199
200 @@ -458,6 +522,7 @@ static const struct imx290_mode imx290_m
201 .link_freq_index = FREQ_INDEX_1080P,
202 .data = imx290_1080p_settings,
203 .data_size = ARRAY_SIZE(imx290_1080p_settings),
204 + .clk_cfg = imx290_1080p_clock_config,
205 },
206 {
207 .width = 1280,
208 @@ -467,6 +532,7 @@ static const struct imx290_mode imx290_m
209 .link_freq_index = FREQ_INDEX_720P,
210 .data = imx290_720p_settings,
211 .data_size = ARRAY_SIZE(imx290_720p_settings),
212 + .clk_cfg = imx290_720p_clock_config,
213 },
214 };
215
216 @@ -592,6 +658,26 @@ static int imx290_set_register_array(str
217 return 0;
218 }
219
220 +static int imx290_set_clock(struct imx290 *imx290)
221 +{
222 + const struct imx290_mode *mode = imx290->current_mode;
223 + enum imx290_clk_freq clk_idx = imx290->xclk_idx;
224 + const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx];
225 + int ret;
226 +
227 + ret = imx290_set_register_array(imx290, xclk_regs[clk_idx],
228 + IMX290_NUM_CLK_REGS);
229 +
230 + imx290_write(imx290, IMX290_INCKSEL1, clk_cfg->incksel1, &ret);
231 + imx290_write(imx290, IMX290_INCKSEL2, clk_cfg->incksel2, &ret);
232 + imx290_write(imx290, IMX290_INCKSEL3, clk_cfg->incksel3, &ret);
233 + imx290_write(imx290, IMX290_INCKSEL4, clk_cfg->incksel4, &ret);
234 + imx290_write(imx290, IMX290_INCKSEL5, clk_cfg->incksel5, &ret);
235 + imx290_write(imx290, IMX290_INCKSEL6, clk_cfg->incksel6, &ret);
236 +
237 + return ret;
238 +}
239 +
240 static int imx290_set_data_lanes(struct imx290 *imx290)
241 {
242 int ret = 0;
243 @@ -896,6 +982,13 @@ static int imx290_start_streaming(struct
244 return ret;
245 }
246
247 + /* Set clock parameters based on mode and xclk */
248 + ret = imx290_set_clock(imx290);
249 + if (ret < 0) {
250 + dev_err(imx290->dev, "Could not set clocks\n");
251 + return ret;
252 + }
253 +
254 /* Set data lane count */
255 ret = imx290_set_data_lanes(imx290);
256 if (ret < 0) {
257 @@ -1295,8 +1388,15 @@ static int imx290_init_clk(struct imx290
258 return ret;
259 }
260
261 - /* external clock must be 37.125 MHz */
262 - if (xclk_freq != 37125000) {
263 + /* external clock must be 37.125 MHz or 74.25MHz */
264 + switch (xclk_freq) {
265 + case 37125000:
266 + imx290->xclk_idx = IMX290_CLK_37_125;
267 + break;
268 + case 74250000:
269 + imx290->xclk_idx = IMX290_CLK_74_25;
270 + break;
271 + default:
272 dev_err(imx290->dev, "External clock frequency %u is not supported\n",
273 xclk_freq);
274 return -EINVAL;
Staging tree of Christian Marangi