df9518d86cd369de2db35f17a6e48a731758646a
[openwrt/staging/ansuel.git] /
1 From 3b00a07c2443745d62babfe08dbb2ad8e649526e Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Fri, 19 Nov 2021 03:03:49 +0100
4 Subject: [PATCH] net: dsa: qca8k: fix internal delay applied to the wrong PAD
5 config
6
7 With SGMII phy the internal delay is always applied to the PAD0 config.
8 This is caused by the falling edge configuration that hardcode the reg
9 to PAD0 (as the falling edge bits are present only in PAD0 reg)
10 Move the delay configuration before the reg overwrite to correctly apply
11 the delay.
12
13 Fixes: cef08115846e ("net: dsa: qca8k: set internal delay also for sgmii")
14 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
15 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
16 Signed-off-by: David S. Miller <davem@davemloft.net>
17 ---
18 drivers/net/dsa/qca8k.c | 12 ++++++------
19 1 file changed, 6 insertions(+), 6 deletions(-)
20
21 --- a/drivers/net/dsa/qca8k.c
22 +++ b/drivers/net/dsa/qca8k.c
23 @@ -1433,6 +1433,12 @@ qca8k_phylink_mac_config(struct dsa_swit
24
25 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
26
27 + /* From original code is reported port instability as SGMII also
28 + * require delay set. Apply advised values here or take them from DT.
29 + */
30 + if (state->interface == PHY_INTERFACE_MODE_SGMII)
31 + qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
32 +
33 /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
34 * falling edge is set writing in the PORT0 PAD reg
35 */
36 @@ -1455,12 +1461,6 @@ qca8k_phylink_mac_config(struct dsa_swit
37 QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
38 val);
39
40 - /* From original code is reported port instability as SGMII also
41 - * require delay set. Apply advised values here or take them from DT.
42 - */
43 - if (state->interface == PHY_INTERFACE_MODE_SGMII)
44 - qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
45 -
46 break;
47 default:
48 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",