1 From 5e339e1502c9be0f624398cf774e5880a6d1a677 Mon Sep 17 00:00:00 2001
2 From: Lee Jackson <lee.jackson@arducam.com>
3 Date: Wed, 10 Jan 2024 09:06:16 +0800
4 Subject: [PATCH] drivers: media: arducam_64mp: Add V4L2_CID_LINK_FREQ control
6 Add V4L2_CID_LINK_FREQ as a read-only control with a value of 456 Mhz.
7 This will be used by the CFE driver to corretly setup the DPHY timing
8 parameters in the CSI-2 block.
10 Signed-off-by: Lee Jackson <lee.jackson@arducam.com>
12 drivers/media/i2c/arducam_64mp.c | 16 ++++++++++++++++
13 1 file changed, 16 insertions(+)
15 --- a/drivers/media/i2c/arducam_64mp.c
16 +++ b/drivers/media/i2c/arducam_64mp.c
17 @@ -143,6 +143,10 @@ struct arducam_64mp_mode {
18 struct arducam_64mp_reg_list reg_list;
21 +static const s64 arducam_64mp_link_freq_menu[] = {
22 + ARDUCAM_64MP_DEFAULT_LINK_FREQ,
25 static const struct arducam_64mp_reg mode_common_regs[] = {
28 @@ -2272,9 +2276,11 @@ static int arducam_64mp_init_controls(st
29 struct v4l2_ctrl_handler *ctrl_hdlr;
30 struct i2c_client *client = v4l2_get_subdevdata(&arducam_64mp->sd);
31 struct v4l2_fwnode_device_properties props;
32 + struct v4l2_ctrl *link_freq;
38 ctrl_hdlr = &arducam_64mp->ctrl_handler;
39 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16);
40 @@ -2292,6 +2298,16 @@ static int arducam_64mp_init_controls(st
41 ARDUCAM_64MP_PIXEL_RATE, 1,
42 ARDUCAM_64MP_PIXEL_RATE);
44 + /* LINK_FREQ is also read only */
45 + link_freq_max = ARRAY_SIZE(arducam_64mp_link_freq_menu) - 1;
47 + v4l2_ctrl_new_int_menu(ctrl_hdlr, &arducam_64mp_ctrl_ops,
50 + arducam_64mp_link_freq_menu);
52 + link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
55 * Create the controls here, but mode specific limits are setup
56 * in the arducam_64mp_set_framing_limits() call below.