git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From 5950c7c0a68c915b336c70f79388626e2d576ab7 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Wed, 2 Feb 2022 01:03:29 +0100
   4 Subject: [PATCH 10/16] net: dsa: qca8k: add support for mgmt read/write in
   5  Ethernet packet
   6
   7 Add qca8k side support for mgmt read/write in Ethernet packet.
   8 qca8k supports some specially crafted Ethernet packet that can be used
   9 for mgmt read/write instead of the legacy method uart/internal mdio.
  10 This add support for the qca8k side to craft the packet and enqueue it.
  11 Each port and the qca8k_priv have a special struct to put data in it.
  12 The completion API is used to wait for the packet to be received back
  13 with the requested data.
  14
  15 The various steps are:
  16 1. Craft the special packet with the qca hdr set to mgmt read/write
  17    mode.
  18 2. Set the lock in the dedicated mgmt struct.
  19 3. Increment the seq number and set it in the mgmt pkt
  20 4. Reinit the completion.
  21 5. Enqueue the packet.
  22 6. Wait the packet to be received.
  23 7. Use the data set by the tagger to complete the mdio operation.
  24
  25 If the completion timeouts or the ack value is not true, the legacy
  26 mdio way is used.
  27
  28 It has to be considered that in the initial setup mdio is still used and
  29 mdio is still used until DSA is ready to accept and tag packet.
  30
  31 tag_proto_connect() is used to fill the required handler for the tagger
  32 to correctly parse and elaborate the special Ethernet mdio packet.
  33
  34 Locking is added to qca8k_master_change() to make sure no mgmt Ethernet
  35 are in progress.
  36
  37 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  38 Signed-off-by: David S. Miller <davem@davemloft.net>
  39 ---
  40  drivers/net/dsa/qca8k.c | 225 ++++++++++++++++++++++++++++++++++++++++
  41  drivers/net/dsa/qca8k.h |  13 +++
  42  2 files changed, 238 insertions(+)
  43
  44 diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
  45 index ec062b9a918d..e3a215f04559 100644
  46 --- a/drivers/net/dsa/qca8k.c
  47 +++ b/drivers/net/dsa/qca8k.c
  48 @@ -20,6 +20,7 @@
  49  #include <linux/phylink.h>
  50  #include <linux/gpio/consumer.h>
  51  #include <linux/etherdevice.h>
  52 +#include <linux/dsa/tag_qca.h>
  53
  54  #include "qca8k.h"
  55
  56 @@ -170,6 +171,194 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
  57         return regmap_update_bits(priv->regmap, reg, mask, write_val);
  58  }
  59
  60 +static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
  61 +{
  62 +       struct qca8k_mgmt_eth_data *mgmt_eth_data;
  63 +       struct qca8k_priv *priv = ds->priv;
  64 +       struct qca_mgmt_ethhdr *mgmt_ethhdr;
  65 +       u8 len, cmd;
  66 +
  67 +       mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb);
  68 +       mgmt_eth_data = &priv->mgmt_eth_data;
  69 +
  70 +       cmd = FIELD_GET(QCA_HDR_MGMT_CMD, mgmt_ethhdr->command);
  71 +       len = FIELD_GET(QCA_HDR_MGMT_LENGTH, mgmt_ethhdr->command);
  72 +
  73 +       /* Make sure the seq match the requested packet */
  74 +       if (mgmt_ethhdr->seq == mgmt_eth_data->seq)
  75 +               mgmt_eth_data->ack = true;
  76 +
  77 +       if (cmd == MDIO_READ) {
  78 +               mgmt_eth_data->data[0] = mgmt_ethhdr->mdio_data;
  79 +
  80 +               /* Get the rest of the 12 byte of data */
  81 +               if (len > QCA_HDR_MGMT_DATA1_LEN)
  82 +                       memcpy(mgmt_eth_data->data + 1, skb->data,
  83 +                              QCA_HDR_MGMT_DATA2_LEN);
  84 +       }
  85 +
  86 +       complete(&mgmt_eth_data->rw_done);
  87 +}
  88 +
  89 +static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,
  90 +                                              int priority)
  91 +{
  92 +       struct qca_mgmt_ethhdr *mgmt_ethhdr;
  93 +       struct sk_buff *skb;
  94 +       u16 hdr;
  95 +
  96 +       skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);
  97 +       if (!skb)
  98 +               return NULL;
  99 +
 100 +       skb_reset_mac_header(skb);
 101 +       skb_set_network_header(skb, skb->len);
 102 +
 103 +       mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);
 104 +
 105 +       hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);
 106 +       hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority);
 107 +       hdr |= QCA_HDR_XMIT_FROM_CPU;
 108 +       hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0));
 109 +       hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);
 110 +
 111 +       mgmt_ethhdr->command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);
 112 +       mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, 4);
 113 +       mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);
 114 +       mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,
 115 +                                          QCA_HDR_MGMT_CHECK_CODE_VAL);
 116 +
 117 +       if (cmd == MDIO_WRITE)
 118 +               mgmt_ethhdr->mdio_data = *val;
 119 +
 120 +       mgmt_ethhdr->hdr = htons(hdr);
 121 +
 122 +       skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);
 123 +
 124 +       return skb;
 125 +}
 126 +
 127 +static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)
 128 +{
 129 +       struct qca_mgmt_ethhdr *mgmt_ethhdr;
 130 +
 131 +       mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data;
 132 +       mgmt_ethhdr->seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);
 133 +}
 134 +
 135 +static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val)
 136 +{
 137 +       struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
 138 +       struct sk_buff *skb;
 139 +       bool ack;
 140 +       int ret;
 141 +
 142 +       skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,
 143 +                                     QCA8K_ETHERNET_MDIO_PRIORITY);
 144 +       if (!skb)
 145 +               return -ENOMEM;
 146 +
 147 +       mutex_lock(&mgmt_eth_data->mutex);
 148 +
 149 +       /* Check mgmt_master if is operational */
 150 +       if (!priv->mgmt_master) {
 151 +               kfree_skb(skb);
 152 +               mutex_unlock(&mgmt_eth_data->mutex);
 153 +               return -EINVAL;
 154 +       }
 155 +
 156 +       skb->dev = priv->mgmt_master;
 157 +
 158 +       reinit_completion(&mgmt_eth_data->rw_done);
 159 +
 160 +       /* Increment seq_num and set it in the mdio pkt */
 161 +       mgmt_eth_data->seq++;
 162 +       qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 163 +       mgmt_eth_data->ack = false;
 164 +
 165 +       dev_queue_xmit(skb);
 166 +
 167 +       ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 168 +                                         msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
 169 +
 170 +       *val = mgmt_eth_data->data[0];
 171 +       ack = mgmt_eth_data->ack;
 172 +
 173 +       mutex_unlock(&mgmt_eth_data->mutex);
 174 +
 175 +       if (ret <= 0)
 176 +               return -ETIMEDOUT;
 177 +
 178 +       if (!ack)
 179 +               return -EINVAL;
 180 +
 181 +       return 0;
 182 +}
 183 +
 184 +static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 val)
 185 +{
 186 +       struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
 187 +       struct sk_buff *skb;
 188 +       bool ack;
 189 +       int ret;
 190 +
 191 +       skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, &val,
 192 +                                     QCA8K_ETHERNET_MDIO_PRIORITY);
 193 +       if (!skb)
 194 +               return -ENOMEM;
 195 +
 196 +       mutex_lock(&mgmt_eth_data->mutex);
 197 +
 198 +       /* Check mgmt_master if is operational */
 199 +       if (!priv->mgmt_master) {
 200 +               kfree_skb(skb);
 201 +               mutex_unlock(&mgmt_eth_data->mutex);
 202 +               return -EINVAL;
 203 +       }
 204 +
 205 +       skb->dev = priv->mgmt_master;
 206 +
 207 +       reinit_completion(&mgmt_eth_data->rw_done);
 208 +
 209 +       /* Increment seq_num and set it in the mdio pkt */
 210 +       mgmt_eth_data->seq++;
 211 +       qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 212 +       mgmt_eth_data->ack = false;
 213 +
 214 +       dev_queue_xmit(skb);
 215 +
 216 +       ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 217 +                                         msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
 218 +
 219 +       ack = mgmt_eth_data->ack;
 220 +
 221 +       mutex_unlock(&mgmt_eth_data->mutex);
 222 +
 223 +       if (ret <= 0)
 224 +               return -ETIMEDOUT;
 225 +
 226 +       if (!ack)
 227 +               return -EINVAL;
 228 +
 229 +       return 0;
 230 +}
 231 +
 232 +static int
 233 +qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
 234 +{
 235 +       u32 val = 0;
 236 +       int ret;
 237 +
 238 +       ret = qca8k_read_eth(priv, reg, &val);
 239 +       if (ret)
 240 +               return ret;
 241 +
 242 +       val &= ~mask;
 243 +       val |= write_val;
 244 +
 245 +       return qca8k_write_eth(priv, reg, val);
 246 +}
 247 +
 248  static int
 249  qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 250  {
 251 @@ -178,6 +367,9 @@ qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 252         u16 r1, r2, page;
 253         int ret;
 254
 255 +       if (!qca8k_read_eth(priv, reg, val))
 256 +               return 0;
 257 +
 258         qca8k_split_addr(reg, &r1, &r2, &page);
 259
 260         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 261 @@ -201,6 +393,9 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 262         u16 r1, r2, page;
 263         int ret;
 264
 265 +       if (!qca8k_write_eth(priv, reg, val))
 266 +               return 0;
 267 +
 268         qca8k_split_addr(reg, &r1, &r2, &page);
 269
 270         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 271 @@ -225,6 +420,9 @@ qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_
 272         u32 val;
 273         int ret;
 274
 275 +       if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
 276 +               return 0;
 277 +
 278         qca8k_split_addr(reg, &r1, &r2, &page);
 279
 280         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 281 @@ -2394,7 +2592,30 @@ qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
 282         if (dp->index != 0)
 283                 return;
 284
 285 +       mutex_lock(&priv->mgmt_eth_data.mutex);
 286 +
 287         priv->mgmt_master = operational ? (struct net_device *)master : NULL;
 288 +
 289 +       mutex_unlock(&priv->mgmt_eth_data.mutex);
 290 +}
 291 +
 292 +static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
 293 +                                     enum dsa_tag_protocol proto)
 294 +{
 295 +       struct qca_tagger_data *tagger_data;
 296 +
 297 +       switch (proto) {
 298 +       case DSA_TAG_PROTO_QCA:
 299 +               tagger_data = ds->tagger_data;
 300 +
 301 +               tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;
 302 +
 303 +               break;
 304 +       default:
 305 +               return -EOPNOTSUPP;
 306 +       }
 307 +
 308 +       return 0;
 309  }
 310
 311  static const struct dsa_switch_ops qca8k_switch_ops = {
 312 @@ -2433,6 +2654,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = {
 313         .port_lag_join          = qca8k_port_lag_join,
 314         .port_lag_leave         = qca8k_port_lag_leave,
 315         .master_state_change    = qca8k_master_change,
 316 +       .connect_tag_protocol   = qca8k_connect_tag_protocol,
 317  };
 318
 319  static int qca8k_read_switch_id(struct qca8k_priv *priv)
 320 @@ -2512,6 +2734,9 @@ qca8k_sw_probe(struct mdio_device *mdiodev)
 321         if (!priv->ds)
 322                 return -ENOMEM;
 323
 324 +       mutex_init(&priv->mgmt_eth_data.mutex);
 325 +       init_completion(&priv->mgmt_eth_data.rw_done);
 326 +
 327         priv->ds->dev = &mdiodev->dev;
 328         priv->ds->num_ports = QCA8K_NUM_PORTS;
 329         priv->ds->priv = priv;
 330 diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
 331 index b81aad98a116..75c28689a652 100644
 332 --- a/drivers/net/dsa/qca8k.h
 333 +++ b/drivers/net/dsa/qca8k.h
 334 @@ -11,6 +11,10 @@
 335  #include <linux/delay.h>
 336  #include <linux/regmap.h>
 337  #include <linux/gpio.h>
 338 +#include <linux/dsa/tag_qca.h>
 339 +
 340 +#define QCA8K_ETHERNET_MDIO_PRIORITY                   7
 341 +#define QCA8K_ETHERNET_TIMEOUT                         100
 342
 343  #define QCA8K_NUM_PORTS                                        7
 344  #define QCA8K_NUM_CPU_PORTS                            2
 345 @@ -328,6 +332,14 @@ enum {
 346         QCA8K_CPU_PORT6,
 347  };
 348
 349 +struct qca8k_mgmt_eth_data {
 350 +       struct completion rw_done;
 351 +       struct mutex mutex; /* Enforce one mdio read/write at time */
 352 +       bool ack;
 353 +       u32 seq;
 354 +       u32 data[4];
 355 +};
 356 +
 357  struct qca8k_ports_config {
 358         bool sgmii_rx_clk_falling_edge;
 359         bool sgmii_tx_clk_falling_edge;
 360 @@ -354,6 +366,7 @@ struct qca8k_priv {
 361         struct gpio_desc *reset_gpio;
 362         unsigned int port_mtu[QCA8K_NUM_PORTS];
 363         struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */
 364 +       struct qca8k_mgmt_eth_data mgmt_eth_data;
 365  };
 366
 367  struct qca8k_mib_desc {
 368 --
 369 2.34.1
 370