deb39477ec73fbc5a8759ec5e6ab87945ea50eb5
[openwrt/staging/ldir.git] /
1 From: Lorenzo Bianconi <lorenzo@kernel.org>
2 Date: Sat, 14 Jan 2023 18:01:29 +0100
3 Subject: [PATCH] net: ethernet: mtk_eth_soc: introduce mtk_hw_warm_reset
4 support
5
6 Introduce mtk_hw_warm_reset utility routine. This is a preliminary patch
7 to align reset procedure to vendor sdk and avoid to power down the chip
8 during hw reset.
9
10 Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
11 Tested-by: Daniel Golle <daniel@makrotopia.org>
12 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
13 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
14 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
15 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
16 ---
17
18 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
19 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
20 @@ -3224,7 +3224,54 @@ static void mtk_hw_reset(struct mtk_eth
21 0x3ffffff);
22 }
23
24 -static int mtk_hw_init(struct mtk_eth *eth)
25 +static u32 mtk_hw_reset_read(struct mtk_eth *eth)
26 +{
27 + u32 val;
28 +
29 + regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val);
30 + return val;
31 +}
32 +
33 +static void mtk_hw_warm_reset(struct mtk_eth *eth)
34 +{
35 + u32 rst_mask, val;
36 +
37 + regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE,
38 + RSTCTRL_FE);
39 + if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val,
40 + val & RSTCTRL_FE, 1, 1000)) {
41 + dev_err(eth->dev, "warm reset failed\n");
42 + mtk_hw_reset(eth);
43 + return;
44 + }
45 +
46 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
47 + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
48 + else
49 + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
50 +
51 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
52 + rst_mask |= RSTCTRL_PPE1;
53 +
54 + regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
55 +
56 + udelay(1);
57 + val = mtk_hw_reset_read(eth);
58 + if (!(val & rst_mask))
59 + dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n",
60 + val, rst_mask);
61 +
62 + rst_mask |= RSTCTRL_FE;
63 + regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask);
64 +
65 + udelay(1);
66 + val = mtk_hw_reset_read(eth);
67 + if (val & rst_mask)
68 + dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n",
69 + val, rst_mask);
70 +}
71 +
72 +static int mtk_hw_init(struct mtk_eth *eth, bool reset)
73 {
74 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
75 ETHSYS_DMA_AG_MAP_PPE;
76 @@ -3263,7 +3310,12 @@ static int mtk_hw_init(struct mtk_eth *e
77 return 0;
78 }
79
80 - mtk_hw_reset(eth);
81 + msleep(100);
82 +
83 + if (reset)
84 + mtk_hw_warm_reset(eth);
85 + else
86 + mtk_hw_reset(eth);
87
88 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
89 /* Set FE to PDMAv2 if necessary */
90 @@ -3451,7 +3503,7 @@ static void mtk_pending_work(struct work
91 if (eth->dev->pins)
92 pinctrl_select_state(eth->dev->pins->p,
93 eth->dev->pins->default_state);
94 - mtk_hw_init(eth);
95 + mtk_hw_init(eth, true);
96
97 /* restart DMA and enable IRQs */
98 for (i = 0; i < MTK_MAC_COUNT; i++) {
99 @@ -4053,7 +4105,7 @@ static int mtk_probe(struct platform_dev
100 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
101 INIT_WORK(&eth->pending_work, mtk_pending_work);
102
103 - err = mtk_hw_init(eth);
104 + err = mtk_hw_init(eth, false);
105 if (err)
106 goto err_wed_exit;
107