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1 From 5654ec78dd7e64b1e04777b24007344329e6a63b Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Thu, 14 Oct 2021 00:39:11 +0200
4 Subject: net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6
5
6 Future proof commit. This switch have 2 CPU ports and one valid
7 configuration is first CPU port set to sgmii and second CPU port set to
8 rgmii-id. The current implementation detects delay only for CPU port
9 zero set to rgmii and doesn't count any delay set in a secondary CPU
10 port. Drop the current delay scan function and move it to the sgmii
11 parser function to generalize and implicitly add support for secondary
12 CPU port set to rgmii-id. Introduce new logic where delay is enabled
13 also with internal delay binding declared and rgmii set as PHY mode.
14
15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
16 Signed-off-by: David S. Miller <davem@davemloft.net>
17 ---
18 drivers/net/dsa/qca8k.c | 165 ++++++++++++++++++++++++------------------------
19 drivers/net/dsa/qca8k.h | 10 ++-
20 2 files changed, 89 insertions(+), 86 deletions(-)
21
22 --- a/drivers/net/dsa/qca8k.c
23 +++ b/drivers/net/dsa/qca8k.c
24 @@ -889,68 +889,6 @@ qca8k_setup_mdio_bus(struct qca8k_priv *
25 }
26
27 static int
28 -qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
29 -{
30 - struct device_node *port_dn;
31 - phy_interface_t mode;
32 - struct dsa_port *dp;
33 - u32 val;
34 -
35 - /* CPU port is already checked */
36 - dp = dsa_to_port(priv->ds, 0);
37 -
38 - port_dn = dp->dn;
39 -
40 - /* Check if port 0 is set to the correct type */
41 - of_get_phy_mode(port_dn, &mode);
42 - if (mode != PHY_INTERFACE_MODE_RGMII_ID &&
43 - mode != PHY_INTERFACE_MODE_RGMII_RXID &&
44 - mode != PHY_INTERFACE_MODE_RGMII_TXID) {
45 - return 0;
46 - }
47 -
48 - switch (mode) {
49 - case PHY_INTERFACE_MODE_RGMII_ID:
50 - case PHY_INTERFACE_MODE_RGMII_RXID:
51 - if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val))
52 - val = 2;
53 - else
54 - /* Switch regs accept value in ns, convert ps to ns */
55 - val = val / 1000;
56 -
57 - if (val > QCA8K_MAX_DELAY) {
58 - dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
59 - val = 3;
60 - }
61 -
62 - priv->rgmii_rx_delay = val;
63 - /* Stop here if we need to check only for rx delay */
64 - if (mode != PHY_INTERFACE_MODE_RGMII_ID)
65 - break;
66 -
67 - fallthrough;
68 - case PHY_INTERFACE_MODE_RGMII_TXID:
69 - if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val))
70 - val = 1;
71 - else
72 - /* Switch regs accept value in ns, convert ps to ns */
73 - val = val / 1000;
74 -
75 - if (val > QCA8K_MAX_DELAY) {
76 - dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
77 - val = 3;
78 - }
79 -
80 - priv->rgmii_tx_delay = val;
81 - break;
82 - default:
83 - return 0;
84 - }
85 -
86 - return 0;
87 -}
88 -
89 -static int
90 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
91 {
92 u32 mask = 0;
93 @@ -996,19 +934,21 @@ static int qca8k_find_cpu_port(struct ds
94 static int
95 qca8k_parse_port_config(struct qca8k_priv *priv)
96 {
97 + int port, cpu_port_index = 0, ret;
98 struct device_node *port_dn;
99 phy_interface_t mode;
100 struct dsa_port *dp;
101 - int port, ret;
102 + u32 delay;
103
104 /* We have 2 CPU port. Check them */
105 - for (port = 0; port < QCA8K_NUM_PORTS; port++) {
106 + for (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {
107 /* Skip every other port */
108 if (port != 0 && port != 6)
109 continue;
110
111 dp = dsa_to_port(priv->ds, port);
112 port_dn = dp->dn;
113 + cpu_port_index++;
114
115 if (!of_device_is_available(port_dn))
116 continue;
117 @@ -1017,12 +957,54 @@ qca8k_parse_port_config(struct qca8k_pri
118 if (ret)
119 continue;
120
121 - if (mode == PHY_INTERFACE_MODE_SGMII) {
122 + switch (mode) {
123 + case PHY_INTERFACE_MODE_RGMII:
124 + case PHY_INTERFACE_MODE_RGMII_ID:
125 + case PHY_INTERFACE_MODE_RGMII_TXID:
126 + case PHY_INTERFACE_MODE_RGMII_RXID:
127 + delay = 0;
128 +
129 + if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
130 + /* Switch regs accept value in ns, convert ps to ns */
131 + delay = delay / 1000;
132 + else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
133 + mode == PHY_INTERFACE_MODE_RGMII_TXID)
134 + delay = 1;
135 +
136 + if (delay > QCA8K_MAX_DELAY) {
137 + dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
138 + delay = 3;
139 + }
140 +
141 + priv->rgmii_tx_delay[cpu_port_index] = delay;
142 +
143 + delay = 0;
144 +
145 + if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
146 + /* Switch regs accept value in ns, convert ps to ns */
147 + delay = delay / 1000;
148 + else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
149 + mode == PHY_INTERFACE_MODE_RGMII_RXID)
150 + delay = 2;
151 +
152 + if (delay > QCA8K_MAX_DELAY) {
153 + dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
154 + delay = 3;
155 + }
156 +
157 + priv->rgmii_rx_delay[cpu_port_index] = delay;
158 +
159 + break;
160 + case PHY_INTERFACE_MODE_SGMII:
161 if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
162 priv->sgmii_tx_clk_falling_edge = true;
163
164 if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
165 priv->sgmii_rx_clk_falling_edge = true;
166 +
167 + break;
168 + default:
169 + continue;
170 }
171 }
172
173 @@ -1059,10 +1041,6 @@ qca8k_setup(struct dsa_switch *ds)
174 if (ret)
175 return ret;
176
177 - ret = qca8k_setup_of_rgmii_delay(priv);
178 - if (ret)
179 - return ret;
180 -
181 ret = qca8k_setup_mac_pwr_sel(priv);
182 if (ret)
183 return ret;
184 @@ -1229,8 +1207,8 @@ qca8k_phylink_mac_config(struct dsa_swit
185 const struct phylink_link_state *state)
186 {
187 struct qca8k_priv *priv = ds->priv;
188 - u32 reg, val;
189 - int ret;
190 + int cpu_port_index, ret;
191 + u32 reg, val, delay;
192
193 switch (port) {
194 case 0: /* 1st CPU port */
195 @@ -1242,6 +1220,7 @@ qca8k_phylink_mac_config(struct dsa_swit
196 return;
197
198 reg = QCA8K_REG_PORT0_PAD_CTRL;
199 + cpu_port_index = QCA8K_CPU_PORT0;
200 break;
201 case 1:
202 case 2:
203 @@ -1260,6 +1239,7 @@ qca8k_phylink_mac_config(struct dsa_swit
204 return;
205
206 reg = QCA8K_REG_PORT6_PAD_CTRL;
207 + cpu_port_index = QCA8K_CPU_PORT6;
208 break;
209 default:
210 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
211 @@ -1274,23 +1254,40 @@ qca8k_phylink_mac_config(struct dsa_swit
212
213 switch (state->interface) {
214 case PHY_INTERFACE_MODE_RGMII:
215 - /* RGMII mode means no delay so don't enable the delay */
216 - qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
217 - break;
218 case PHY_INTERFACE_MODE_RGMII_ID:
219 case PHY_INTERFACE_MODE_RGMII_TXID:
220 case PHY_INTERFACE_MODE_RGMII_RXID:
221 - /* RGMII_ID needs internal delay. This is enabled through
222 - * PORT5_PAD_CTRL for all ports, rather than individual port
223 - * registers
224 + val = QCA8K_PORT_PAD_RGMII_EN;
225 +
226 + /* Delay can be declared in 3 different way.
227 + * Mode to rgmii and internal-delay standard binding defined
228 + * rgmii-id or rgmii-tx/rx phy mode set.
229 + * The parse logic set a delay different than 0 only when one
230 + * of the 3 different way is used. In all other case delay is
231 + * not enabled. With ID or TX/RXID delay is enabled and set
232 + * to the default and recommended value.
233 + */
234 + if (priv->rgmii_tx_delay[cpu_port_index]) {
235 + delay = priv->rgmii_tx_delay[cpu_port_index];
236 +
237 + val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
238 + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
239 + }
240 +
241 + if (priv->rgmii_rx_delay[cpu_port_index]) {
242 + delay = priv->rgmii_rx_delay[cpu_port_index];
243 +
244 + val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
245 + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
246 + }
247 +
248 + /* Set RGMII delay based on the selected values */
249 + qca8k_write(priv, reg, val);
250 +
251 + /* QCA8337 requires to set rgmii rx delay for all ports.
252 + * This is enabled through PORT5_PAD_CTRL for all ports,
253 + * rather than individual port registers.
254 */
255 - qca8k_write(priv, reg,
256 - QCA8K_PORT_PAD_RGMII_EN |
257 - QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
258 - QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
259 - QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
260 - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
261 - /* QCA8337 requires to set rgmii rx delay */
262 if (priv->switch_id == QCA8K_ID_QCA8337)
263 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
264 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
265 --- a/drivers/net/dsa/qca8k.h
266 +++ b/drivers/net/dsa/qca8k.h
267 @@ -13,6 +13,7 @@
268 #include <linux/gpio.h>
269
270 #define QCA8K_NUM_PORTS 7
271 +#define QCA8K_NUM_CPU_PORTS 2
272 #define QCA8K_MAX_MTU 9000
273
274 #define PHY_ID_QCA8327 0x004dd034
275 @@ -255,13 +256,18 @@ struct qca8k_match_data {
276 u8 id;
277 };
278
279 +enum {
280 + QCA8K_CPU_PORT0,
281 + QCA8K_CPU_PORT6,
282 +};
283 +
284 struct qca8k_priv {
285 u8 switch_id;
286 u8 switch_revision;
287 - u8 rgmii_tx_delay;
288 - u8 rgmii_rx_delay;
289 bool sgmii_rx_clk_falling_edge;
290 bool sgmii_tx_clk_falling_edge;
291 + u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
292 + u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
293 bool legacy_phy_port_mapping;
294 struct regmap *regmap;
295 struct mii_bus *bus;
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