git.openwrt.org Git - openwrt/staging/dangole.git/blob

   1 From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001
   2 From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
   3 Date: Thu, 14 Sep 2023 12:29:57 +0530
   4 Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock
   5  provider
   6
   7 While the kernel is booting up, APSS PLL will be running at 800MHz with
   8 GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
   9 configured and select the rate based on the opp table and the source will
  10 be changed to APSS_PLL_EARLY.
  11
  12 Without this patch, CPU Freq driver reports that CPU is running at 24MHz
  13 instead of the 800MHz.
  14
  15 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  16 Tested-by: Robert Marko <robimarko@gmail.com>
  17 Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
  18 ---
  19  drivers/clk/qcom/apss-ipq6018.c | 3 +++
  20  1 file changed, 3 insertions(+)
  21
  22 --- a/drivers/clk/qcom/apss-ipq6018.c
  23 +++ b/drivers/clk/qcom/apss-ipq6018.c
  24 @@ -20,16 +20,19 @@
  25
  26  enum {
  27         P_XO,
  28 +       P_GPLL0,
  29         P_APSS_PLL_EARLY,
  30  };
  31
  32  static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
  33         { .fw_name = "xo" },
  34 +       { .fw_name = "gpll0" },
  35         { .fw_name = "pll" },
  36  };
  37
  38  static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
  39         { P_XO, 0 },
  40 +       { P_GPLL0, 4 },
  41         { P_APSS_PLL_EARLY, 5 },
  42  };
  43