1 From 7ca989eafbd6ce1c216a775556c4893baab1959b Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
3 Date: Wed, 24 Mar 2021 09:19:13 +0100
4 Subject: [PATCH 12/22] dt-bindings: add BCM6362 GPIO sysctl binding
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
10 Add binding documentation for the GPIO sysctl found in BCM6362 SoCs.
12 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
13 Reviewed-by: Rob Herring <robh@kernel.org>
14 Link: https://lore.kernel.org/r/20210324081923.20379-13-noltari@gmail.com
15 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
17 .../mfd/brcm,bcm6362-gpio-sysctl.yaml | 236 ++++++++++++++++++
18 1 file changed, 236 insertions(+)
19 create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml
22 +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml
24 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
27 +$id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
28 +$schema: http://devicetree.org/meta-schemas/core.yaml#
30 +title: Broadcom BCM6362 GPIO System Controller Device Tree Bindings
33 + - Álvaro Fernández Rojas <noltari@gmail.com>
34 + - Jonas Gorski <jonas.gorski@gmail.com>
37 + Broadcom BCM6362 SoC GPIO system controller which provides a register map
38 + for controlling the GPIO and pins of the SoC.
41 + "#address-cells": true
47 + - const: brcm,bcm6362-gpio-sysctl
61 + $ref: "../gpio/brcm,bcm6345-gpio.yaml"
63 + GPIO controller for the SoC GPIOs. This child node definition
64 + should follow the bindings specified in
65 + Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
67 + "^pinctrl@[0-9a-f]+$":
70 + $ref: "../pinctrl/brcm,bcm6362-pinctrl.yaml"
72 + Pin controller for the SoC pins. This child node definition
73 + should follow the bindings specified in
74 + Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml.
83 +additionalProperties: false
88 + #address-cells = <1>;
90 + compatible = "brcm,bcm6362-gpio-sysctl", "syscon", "simple-mfd";
91 + reg = <0x10000080 0x80>;
92 + ranges = <0 0x10000080 0x80>;
95 + compatible = "brcm,bcm6362-gpio";
96 + reg-names = "dirout", "dat";
97 + reg = <0x0 0x8>, <0x8 0x8>;
100 + gpio-ranges = <&pinctrl 0 0 48>;
104 + pinctrl: pinctrl@18 {
105 + compatible = "brcm,bcm6362-pinctrl";
106 + reg = <0x18 0x10>, <0x38 0x4>;
108 + pinctrl_usb_device_led: usb_device_led-pins {
109 + function = "usb_device_led";
113 + pinctrl_sys_irq: sys_irq-pins {
114 + function = "sys_irq";
118 + pinctrl_serial_led: serial_led-pins {
119 + pinctrl_serial_led_clk: serial_led_clk-pins {
120 + function = "serial_led_clk";
124 + pinctrl_serial_led_data: serial_led_data-pins {
125 + function = "serial_led_data";
130 + pinctrl_robosw_led_data: robosw_led_data-pins {
131 + function = "robosw_led_data";
135 + pinctrl_robosw_led_clk: robosw_led_clk-pins {
136 + function = "robosw_led_clk";
140 + pinctrl_robosw_led0: robosw_led0-pins {
141 + function = "robosw_led0";
145 + pinctrl_robosw_led1: robosw_led1-pins {
146 + function = "robosw_led1";
150 + pinctrl_inet_led: inet_led-pins {
151 + function = "inet_led";
155 + pinctrl_spi_cs2: spi_cs2-pins {
156 + function = "spi_cs2";
160 + pinctrl_spi_cs3: spi_cs3-pins {
161 + function = "spi_cs3";
165 + pinctrl_ntr_pulse: ntr_pulse-pins {
166 + function = "ntr_pulse";
170 + pinctrl_uart1_scts: uart1_scts-pins {
171 + function = "uart1_scts";
175 + pinctrl_uart1_srts: uart1_srts-pins {
176 + function = "uart1_srts";
180 + pinctrl_uart1: uart1-pins {
181 + pinctrl_uart1_sdin: uart1_sdin-pins {
182 + function = "uart1_sdin";
186 + pinctrl_uart1_sdout: uart1_sdout-pins {
187 + function = "uart1_sdout";
192 + pinctrl_adsl_spi: adsl_spi-pins {
193 + pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
194 + function = "adsl_spi_miso";
198 + pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
199 + function = "adsl_spi_mosi";
203 + pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
204 + function = "adsl_spi_clk";
208 + pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
209 + function = "adsl_spi_cs";
214 + pinctrl_ephy0_led: ephy0_led-pins {
215 + function = "ephy0_led";
219 + pinctrl_ephy1_led: ephy1_led-pins {
220 + function = "ephy1_led";
224 + pinctrl_ephy2_led: ephy2_led-pins {
225 + function = "ephy2_led";
229 + pinctrl_ephy3_led: ephy3_led-pins {
230 + function = "ephy3_led";
234 + pinctrl_ext_irq0: ext_irq0-pins {
235 + function = "ext_irq0";
239 + pinctrl_ext_irq1: ext_irq1-pins {
240 + function = "ext_irq1";
244 + pinctrl_ext_irq2: ext_irq2-pins {
245 + function = "ext_irq2";
249 + pinctrl_ext_irq3: ext_irq3-pins {
250 + function = "ext_irq3";
254 + pinctrl_nand: nand-pins {
256 + group = "nand_grp";