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1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
2 Subject: [PATCH 2/2] net: phy: pick Broadcom drivers updates from net-next for
3 4.11
4 MIME-Version: 1.0
5 Content-Type: text/plain; charset=UTF-8
6 Content-Transfer-Encoding: 8bit
7
8 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
9 ---
10
11 --- a/drivers/net/phy/bcm7xxx.c
12 +++ b/drivers/net/phy/bcm7xxx.c
13 @@ -163,12 +163,43 @@ static int bcm7xxx_28nm_e0_plus_afe_conf
14 return 0;
15 }
16
17 +static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
18 +{
19 + /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
20 + bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
21 +
22 + /* Cut master bias current by 2% to compensate for RC_CAL offset */
23 + bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
24 +
25 + /* Improve hybrid leakage */
26 + bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
27 +
28 + /* Change rx_on_tune 8 to 0xf */
29 + bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
30 +
31 + /* Change 100Tx EEE bandwidth */
32 + bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
33 +
34 + /* Enable ffe zero detection for Vitesse interoperability */
35 + bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
36 +
37 + r_rc_cal_reset(phydev);
38 +
39 + return 0;
40 +}
41 +
42 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
43 {
44 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
45 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
46 int ret = 0;
47
48 + /* Newer devices have moved the revision information back into a
49 + * standard location in MII_PHYS_ID[23]
50 + */
51 + if (rev == 0)
52 + rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
53 +
54 pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
55 dev_name(&phydev->dev), phydev->drv->name, rev, patch);
56
57 @@ -192,6 +223,9 @@ static int bcm7xxx_28nm_config_init(stru
58 case 0x10:
59 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
60 break;
61 + case 0x01:
62 + ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
63 + break;
64 default:
65 break;
66 }
67 @@ -336,6 +370,7 @@ static int bcm7xxx_suspend(struct phy_de
68
69 static struct phy_driver bcm7xxx_driver[] = {
70 BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
71 + BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
72 BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
73 BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
74 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
75 @@ -350,6 +385,7 @@ static struct phy_driver bcm7xxx_driver[
76
77 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
78 { PHY_ID_BCM7250, 0xfffffff0, },
79 + { PHY_ID_BCM7278, 0xfffffff0, },
80 { PHY_ID_BCM7364, 0xfffffff0, },
81 { PHY_ID_BCM7366, 0xfffffff0, },
82 { PHY_ID_BCM7346, 0xfffffff0, },
83 --- a/drivers/net/phy/broadcom.c
84 +++ b/drivers/net/phy/broadcom.c
85 @@ -30,6 +30,22 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
86 MODULE_AUTHOR("Maciej W. Rozycki");
87 MODULE_LICENSE("GPL");
88
89 +static int bcm54210e_config_init(struct phy_device *phydev)
90 +{
91 + int val;
92 +
93 + val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
94 + val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
95 + val |= MII_BCM54XX_AUXCTL_MISC_WREN;
96 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
97 +
98 + val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
99 + val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
100 + bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
101 +
102 + return 0;
103 +}
104 +
105 static int bcm54810_config(struct phy_device *phydev)
106 {
107 int rc, val;
108 @@ -230,7 +246,11 @@ static int bcm54xx_config_init(struct ph
109 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
110 bcm54xx_adjust_rxrefclk(phydev);
111
112 - if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
113 + if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
114 + err = bcm54210e_config_init(phydev);
115 + if (err)
116 + return err;
117 + } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
118 err = bcm54810_config(phydev);
119 if (err)
120 return err;
121 @@ -395,12 +415,10 @@ static int bcm54612e_config_aneg(struct
122 (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
123 u16 reg;
124
125 - /* Errata: reads require filling in the write selector field */
126 - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
127 - MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
128 - reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
129 + reg = bcm54xx_auxctl_read(phydev,
130 + MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
131 /* Disable RXD to RXC delay (default set) */
132 - reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
133 + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
134 /* Clear shadow selector field */
135 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
136 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
137 @@ -548,6 +566,17 @@ static struct phy_driver broadcom_driver
138 .config_intr = bcm_phy_config_intr,
139 .driver = { .owner = THIS_MODULE },
140 }, {
141 + .phy_id = PHY_ID_BCM54210E,
142 + .phy_id_mask = 0xfffffff0,
143 + .name = "Broadcom BCM54210E",
144 + .features = PHY_GBIT_FEATURES,
145 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
146 + .config_init = bcm54xx_config_init,
147 + .config_aneg = genphy_config_aneg,
148 + .read_status = genphy_read_status,
149 + .ack_interrupt = bcm_phy_ack_intr,
150 + .config_intr = bcm_phy_config_intr,
151 +}, {
152 .phy_id = PHY_ID_BCM5461,
153 .phy_id_mask = 0xfffffff0,
154 .name = "Broadcom BCM5461",
155 @@ -708,6 +737,7 @@ module_phy_driver(broadcom_drivers);
156 static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
157 { PHY_ID_BCM5411, 0xfffffff0 },
158 { PHY_ID_BCM5421, 0xfffffff0 },
159 + { PHY_ID_BCM54210E, 0xfffffff0 },
160 { PHY_ID_BCM5461, 0xfffffff0 },
161 { PHY_ID_BCM54612E, 0xfffffff0 },
162 { PHY_ID_BCM54616S, 0xfffffff0 },
163 --- a/include/linux/brcmphy.h
164 +++ b/include/linux/brcmphy.h
165 @@ -17,6 +17,7 @@
166 #define PHY_ID_BCM5482 0x0143bcb0
167 #define PHY_ID_BCM5411 0x00206070
168 #define PHY_ID_BCM5421 0x002060e0
169 +#define PHY_ID_BCM54210E 0x600d84a0
170 #define PHY_ID_BCM5464 0x002060b0
171 #define PHY_ID_BCM5461 0x002060c0
172 #define PHY_ID_BCM54612E 0x03625e60
173 @@ -24,6 +25,7 @@
174 #define PHY_ID_BCM57780 0x03625d90
175
176 #define PHY_ID_BCM7250 0xae025280
177 +#define PHY_ID_BCM7278 0xae0251a0
178 #define PHY_ID_BCM7364 0xae025260
179 #define PHY_ID_BCM7366 0x600d8490
180 #define PHY_ID_BCM7346 0x600d8650
181 @@ -103,18 +105,17 @@
182 /*
183 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
184 */
185 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
186 +#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
187 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
188 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
189
190 -#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
191 -#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
192 -#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
193 -#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
194 -#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
195 -#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
196 -#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
197 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
198 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
199 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
200 +#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
201 +#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
202
203 +#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
204 #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
205
206 /*
Staging tree of Petr Stetiar