d7ee96a3884ea72c858432afafba5af5390b96b5
[openwrt/staging/ynezz.git] /
1 From a563dccef2871e37efcfcb2f3faee7c9f9381f6c Mon Sep 17 00:00:00 2001
2 From: Calvin Johnson <calvin.johnson@nxp.com>
3 Date: Wed, 20 Jun 2018 10:23:41 +0530
4 Subject: [PATCH] staging: fsl_ppfe/eth: handle ls1012a errata_a010897
5
6 On LS1012A rev 1.0, Jumbo frames are not supported as it causes
7 the PFE controller to hang. A reset of the entire chip is required
8 to resume normal operation.
9
10 To handle this errata, frames with length > 1900 are truncated for
11 rev 1.0 of LS1012A.
12
13 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
14 ---
15 drivers/staging/fsl_ppfe/pfe_eth.c | 20 +++++++++++++++++++-
16 drivers/staging/fsl_ppfe/pfe_eth.h | 3 ++-
17 drivers/staging/fsl_ppfe/pfe_hal.c | 10 +++++++++-
18 3 files changed, 30 insertions(+), 3 deletions(-)
19
20 --- a/drivers/staging/fsl_ppfe/pfe_eth.c
21 +++ b/drivers/staging/fsl_ppfe/pfe_eth.c
22 @@ -44,6 +44,7 @@
23 #include <linux/delay.h>
24 #include <linux/regmap.h>
25 #include <linux/i2c.h>
26 +#include <linux/fsl/guts.h>
27
28 #if defined(CONFIG_NF_CONNTRACK_MARK)
29 #include <net/netfilter/nf_conntrack.h>
30 @@ -52,6 +53,10 @@
31 #include "pfe_mod.h"
32 #include "pfe_eth.h"
33
34 +#define LS1012A_REV_1_0 0x87040010
35 +
36 +bool pfe_errata_a010897;
37 +
38 static void *cbus_emac_base[3];
39 static void *cbus_gpi_base[3];
40
41 @@ -2362,7 +2367,15 @@ static int pfe_eth_init_one(struct pfe *
42
43 /* Set MTU limits */
44 ndev->min_mtu = ETH_MIN_MTU;
45 - ndev->max_mtu = JUMBO_FRAME_SIZE;
46 +
47 +/*
48 + * Jumbo frames are not supported on LS1012A rev-1.0.
49 + * So max mtu should be restricted to supported frame length.
50 + */
51 + if (pfe_errata_a010897)
52 + ndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN;
53 + else
54 + ndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN;
55
56 /* supported features */
57 ndev->hw_features = NETIF_F_SG;
58 @@ -2453,6 +2466,11 @@ int pfe_eth_init(struct pfe *pfe)
59 cbus_gpi_base[0] = EGPI1_BASE_ADDR;
60 cbus_gpi_base[1] = EGPI2_BASE_ADDR;
61
62 + if (fsl_guts_get_svr() == LS1012A_REV_1_0)
63 + pfe_errata_a010897 = true;
64 + else
65 + pfe_errata_a010897 = false;
66 +
67 for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
68 err = pfe_eth_init_one(pfe, ii);
69 if (err)
70 --- a/drivers/staging/fsl_ppfe/pfe_eth.h
71 +++ b/drivers/staging/fsl_ppfe/pfe_eth.h
72 @@ -85,7 +85,8 @@ struct ls1012a_pfe_platform_data {
73 #define EMAC_TXQ_CNT 16
74 #define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT)
75
76 -#define JUMBO_FRAME_SIZE 10258
77 +#define JUMBO_FRAME_SIZE_V1 1900
78 +#define JUMBO_FRAME_SIZE_V2 10258
79 /*
80 * Client Tx queue threshold, for txQ flush condition.
81 * It must be smaller than the queue size (in case we ever change it in the
82 --- a/drivers/staging/fsl_ppfe/pfe_hal.c
83 +++ b/drivers/staging/fsl_ppfe/pfe_hal.c
84 @@ -19,6 +19,9 @@
85 #include "pfe_mod.h"
86 #include "pfe/pfe.h"
87
88 +/* A-010897: Jumbo frame is not supported */
89 +extern bool pfe_errata_a010897;
90 +
91 #define PFE_RCR_MAX_FL_MASK 0xC000FFFF
92
93 void *cbus_base_addr;
94 @@ -1102,7 +1105,12 @@ void gemac_set_config(void *base, struct
95 /*GEMAC config taken from VLSI */
96 writel(0x00000004, base + EMAC_TFWR_STR_FWD);
97 writel(0x00000005, base + EMAC_RX_SECTION_FULL);
98 - writel(0x00003fff, base + EMAC_TRUNC_FL);
99 +
100 + if (pfe_errata_a010897)
101 + writel(0x0000076c, base + EMAC_TRUNC_FL);
102 + else
103 + writel(0x00003fff, base + EMAC_TRUNC_FL);
104 +
105 writel(0x00000030, base + EMAC_TX_SECTION_EMPTY);
106 writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);
107