git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001
   2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   3 Date: Fri, 20 Jan 2023 10:20:53 +0100
   4 Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to
   5  mtk_clk_simple_probe()
   6
   7 There are no more non-common calls in clk_mt7986_topckgen_probe():
   8 migrate this driver to mtk_clk_simple_probe().
   9
  10 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  11 Reviewed-by: Miles Chen <miles.chen@mediatek.com>
  12 Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
  13 Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com
  14 Tested-by: Mingming Su <mingming.su@mediatek.com>
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++-----------------
  18  1 file changed, 13 insertions(+), 42 deletions(-)
  19
  20 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
  21 +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
  22 @@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[]
  23                              0x1C4, 5),
  24  };
  25
  26 -static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
  27 -{
  28 -       struct clk_hw_onecell_data *clk_data;
  29 -       struct device_node *node = pdev->dev.of_node;
  30 -       int r;
  31 -       void __iomem *base;
  32 -       int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
  33 -                ARRAY_SIZE(top_muxes);
  34 -
  35 -       base = of_iomap(node, 0);
  36 -       if (!base) {
  37 -               pr_err("%s(): ioremap failed\n", __func__);
  38 -               return -ENOMEM;
  39 -       }
  40 -
  41 -       clk_data = mtk_alloc_clk_data(nr);
  42 -       if (!clk_data)
  43 -               return -ENOMEM;
  44 -
  45 -       mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  46 -                                   clk_data);
  47 -       mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
  48 -       mtk_clk_register_muxes(&pdev->dev, top_muxes,
  49 -                              ARRAY_SIZE(top_muxes), node,
  50 -                              &mt7986_clk_lock, clk_data);
  51 -
  52 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  53 -
  54 -       if (r) {
  55 -               pr_err("%s(): could not register clock provider: %d\n",
  56 -                      __func__, r);
  57 -               goto free_topckgen_data;
  58 -       }
  59 -       return r;
  60 -
  61 -free_topckgen_data:
  62 -       mtk_free_clk_data(clk_data);
  63 -       return r;
  64 -}
  65 +static const struct mtk_clk_desc topck_desc = {
  66 +       .fixed_clks = top_fixed_clks,
  67 +       .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
  68 +       .factor_clks = top_divs,
  69 +       .num_factor_clks = ARRAY_SIZE(top_divs),
  70 +       .mux_clks = top_muxes,
  71 +       .num_mux_clks = ARRAY_SIZE(top_muxes),
  72 +       .clk_lock = &mt7986_clk_lock,
  73 +};
  74
  75  static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
  76 -       { .compatible = "mediatek,mt7986-topckgen", },
  77 -       {}
  78 +       { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc },
  79 +       { /* sentinel */ }
  80  };
  81
  82  static struct platform_driver clk_mt7986_topckgen_drv = {
  83 -       .probe = clk_mt7986_topckgen_probe,
  84 +       .probe = mtk_clk_simple_probe,
  85 +       .remove = mtk_clk_simple_remove,
  86         .driver = {
  87                 .name = "clk-mt7986-topckgen",
  88                 .of_match_table = of_match_clk_mt7986_topckgen,