git.openwrt.org Git - openwrt/staging/mkresin.git/blob

   1 From 56d254c9b7abf3e5632dd1b257927e23b4449019 Mon Sep 17 00:00:00 2001
   2 From: Dong Aisheng <aisheng.dong@nxp.com>
   3 Date: Fri, 16 Aug 2019 18:01:43 +0800
   4 Subject: [PATCH] Revert "ASoC: fsl_sai: Add registers definition for multiple
   5  datalines"
   6
   7 This reverts commit 5f0ac20ed6db1d6da2eea8b862cf3d54fdfb5830.
   8 ---
   9  sound/soc/fsl/fsl_sai.c | 76 +++++++------------------------------------------
  10  sound/soc/fsl/fsl_sai.h | 36 +++--------------------
  11  2 files changed, 14 insertions(+), 98 deletions(-)
  12
  13 --- a/sound/soc/fsl/fsl_sai.c
  14 +++ b/sound/soc/fsl/fsl_sai.c
  15 @@ -685,14 +685,7 @@ static struct reg_default fsl_sai_reg_de
  16         {FSL_SAI_TCR3, 0},
  17         {FSL_SAI_TCR4, 0},
  18         {FSL_SAI_TCR5, 0},
  19 -       {FSL_SAI_TDR0, 0},
  20 -       {FSL_SAI_TDR1, 0},
  21 -       {FSL_SAI_TDR2, 0},
  22 -       {FSL_SAI_TDR3, 0},
  23 -       {FSL_SAI_TDR4, 0},
  24 -       {FSL_SAI_TDR5, 0},
  25 -       {FSL_SAI_TDR6, 0},
  26 -       {FSL_SAI_TDR7, 0},
  27 +       {FSL_SAI_TDR,  0},
  28         {FSL_SAI_TMR,  0},
  29         {FSL_SAI_RCR1, 0},
  30         {FSL_SAI_RCR2, 0},
  31 @@ -711,14 +704,7 @@ static bool fsl_sai_readable_reg(struct
  32         case FSL_SAI_TCR3:
  33         case FSL_SAI_TCR4:
  34         case FSL_SAI_TCR5:
  35 -       case FSL_SAI_TFR0:
  36 -       case FSL_SAI_TFR1:
  37 -       case FSL_SAI_TFR2:
  38 -       case FSL_SAI_TFR3:
  39 -       case FSL_SAI_TFR4:
  40 -       case FSL_SAI_TFR5:
  41 -       case FSL_SAI_TFR6:
  42 -       case FSL_SAI_TFR7:
  43 +       case FSL_SAI_TFR:
  44         case FSL_SAI_TMR:
  45         case FSL_SAI_RCSR:
  46         case FSL_SAI_RCR1:
  47 @@ -726,22 +712,8 @@ static bool fsl_sai_readable_reg(struct
  48         case FSL_SAI_RCR3:
  49         case FSL_SAI_RCR4:
  50         case FSL_SAI_RCR5:
  51 -       case FSL_SAI_RDR0:
  52 -       case FSL_SAI_RDR1:
  53 -       case FSL_SAI_RDR2:
  54 -       case FSL_SAI_RDR3:
  55 -       case FSL_SAI_RDR4:
  56 -       case FSL_SAI_RDR5:
  57 -       case FSL_SAI_RDR6:
  58 -       case FSL_SAI_RDR7:
  59 -       case FSL_SAI_RFR0:
  60 -       case FSL_SAI_RFR1:
  61 -       case FSL_SAI_RFR2:
  62 -       case FSL_SAI_RFR3:
  63 -       case FSL_SAI_RFR4:
  64 -       case FSL_SAI_RFR5:
  65 -       case FSL_SAI_RFR6:
  66 -       case FSL_SAI_RFR7:
  67 +       case FSL_SAI_RDR:
  68 +       case FSL_SAI_RFR:
  69         case FSL_SAI_RMR:
  70                 return true;
  71         default:
  72 @@ -754,30 +726,9 @@ static bool fsl_sai_volatile_reg(struct
  73         switch (reg) {
  74         case FSL_SAI_TCSR:
  75         case FSL_SAI_RCSR:
  76 -       case FSL_SAI_TFR0:
  77 -       case FSL_SAI_TFR1:
  78 -       case FSL_SAI_TFR2:
  79 -       case FSL_SAI_TFR3:
  80 -       case FSL_SAI_TFR4:
  81 -       case FSL_SAI_TFR5:
  82 -       case FSL_SAI_TFR6:
  83 -       case FSL_SAI_TFR7:
  84 -       case FSL_SAI_RFR0:
  85 -       case FSL_SAI_RFR1:
  86 -       case FSL_SAI_RFR2:
  87 -       case FSL_SAI_RFR3:
  88 -       case FSL_SAI_RFR4:
  89 -       case FSL_SAI_RFR5:
  90 -       case FSL_SAI_RFR6:
  91 -       case FSL_SAI_RFR7:
  92 -       case FSL_SAI_RDR0:
  93 -       case FSL_SAI_RDR1:
  94 -       case FSL_SAI_RDR2:
  95 -       case FSL_SAI_RDR3:
  96 -       case FSL_SAI_RDR4:
  97 -       case FSL_SAI_RDR5:
  98 -       case FSL_SAI_RDR6:
  99 -       case FSL_SAI_RDR7:
 100 +       case FSL_SAI_TFR:
 101 +       case FSL_SAI_RFR:
 102 +       case FSL_SAI_RDR:
 103                 return true;
 104         default:
 105                 return false;
 106 @@ -793,14 +744,7 @@ static bool fsl_sai_writeable_reg(struct
 107         case FSL_SAI_TCR3:
 108         case FSL_SAI_TCR4:
 109         case FSL_SAI_TCR5:
 110 -       case FSL_SAI_TDR0:
 111 -       case FSL_SAI_TDR1:
 112 -       case FSL_SAI_TDR2:
 113 -       case FSL_SAI_TDR3:
 114 -       case FSL_SAI_TDR4:
 115 -       case FSL_SAI_TDR5:
 116 -       case FSL_SAI_TDR6:
 117 -       case FSL_SAI_TDR7:
 118 +       case FSL_SAI_TDR:
 119         case FSL_SAI_TMR:
 120         case FSL_SAI_RCSR:
 121         case FSL_SAI_RCR1:
 122 @@ -942,8 +886,8 @@ static int fsl_sai_probe(struct platform
 123                                    MCLK_DIR(index));
 124         }
 125
 126 -       sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
 127 -       sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
 128 +       sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
 129 +       sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
 130         sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
 131         sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
 132
 133 --- a/sound/soc/fsl/fsl_sai.h
 134 +++ b/sound/soc/fsl/fsl_sai.h
 135 @@ -20,22 +20,8 @@
 136  #define FSL_SAI_TCR3   0x0c /* SAI Transmit Configuration 3 */
 137  #define FSL_SAI_TCR4   0x10 /* SAI Transmit Configuration 4 */
 138  #define FSL_SAI_TCR5   0x14 /* SAI Transmit Configuration 5 */
 139 -#define FSL_SAI_TDR0   0x20 /* SAI Transmit Data 0 */
 140 -#define FSL_SAI_TDR1   0x24 /* SAI Transmit Data 1 */
 141 -#define FSL_SAI_TDR2   0x28 /* SAI Transmit Data 2 */
 142 -#define FSL_SAI_TDR3   0x2C /* SAI Transmit Data 3 */
 143 -#define FSL_SAI_TDR4   0x30 /* SAI Transmit Data 4 */
 144 -#define FSL_SAI_TDR5   0x34 /* SAI Transmit Data 5 */
 145 -#define FSL_SAI_TDR6   0x38 /* SAI Transmit Data 6 */
 146 -#define FSL_SAI_TDR7   0x3C /* SAI Transmit Data 7 */
 147 -#define FSL_SAI_TFR0   0x40 /* SAI Transmit FIFO 0 */
 148 -#define FSL_SAI_TFR1   0x44 /* SAI Transmit FIFO 1 */
 149 -#define FSL_SAI_TFR2   0x48 /* SAI Transmit FIFO 2 */
 150 -#define FSL_SAI_TFR3   0x4C /* SAI Transmit FIFO 3 */
 151 -#define FSL_SAI_TFR4   0x50 /* SAI Transmit FIFO 4 */
 152 -#define FSL_SAI_TFR5   0x54 /* SAI Transmit FIFO 5 */
 153 -#define FSL_SAI_TFR6   0x58 /* SAI Transmit FIFO 6 */
 154 -#define FSL_SAI_TFR7   0x5C /* SAI Transmit FIFO 7 */
 155 +#define FSL_SAI_TDR    0x20 /* SAI Transmit Data */
 156 +#define FSL_SAI_TFR    0x40 /* SAI Transmit FIFO */
 157  #define FSL_SAI_TMR    0x60 /* SAI Transmit Mask */
 158  #define FSL_SAI_RCSR   0x80 /* SAI Receive Control */
 159  #define FSL_SAI_RCR1   0x84 /* SAI Receive Configuration 1 */
 160 @@ -43,22 +29,8 @@
 161  #define FSL_SAI_RCR3   0x8c /* SAI Receive Configuration 3 */
 162  #define FSL_SAI_RCR4   0x90 /* SAI Receive Configuration 4 */
 163  #define FSL_SAI_RCR5   0x94 /* SAI Receive Configuration 5 */
 164 -#define FSL_SAI_RDR0   0xa0 /* SAI Receive Data 0 */
 165 -#define FSL_SAI_RDR1   0xa4 /* SAI Receive Data 1 */
 166 -#define FSL_SAI_RDR2   0xa8 /* SAI Receive Data 2 */
 167 -#define FSL_SAI_RDR3   0xac /* SAI Receive Data 3 */
 168 -#define FSL_SAI_RDR4   0xb0 /* SAI Receive Data 4 */
 169 -#define FSL_SAI_RDR5   0xb4 /* SAI Receive Data 5 */
 170 -#define FSL_SAI_RDR6   0xb8 /* SAI Receive Data 6 */
 171 -#define FSL_SAI_RDR7   0xbc /* SAI Receive Data 7 */
 172 -#define FSL_SAI_RFR0   0xc0 /* SAI Receive FIFO 0 */
 173 -#define FSL_SAI_RFR1   0xc4 /* SAI Receive FIFO 1 */
 174 -#define FSL_SAI_RFR2   0xc8 /* SAI Receive FIFO 2 */
 175 -#define FSL_SAI_RFR3   0xcc /* SAI Receive FIFO 3 */
 176 -#define FSL_SAI_RFR4   0xd0 /* SAI Receive FIFO 4 */
 177 -#define FSL_SAI_RFR5   0xd4 /* SAI Receive FIFO 5 */
 178 -#define FSL_SAI_RFR6   0xd8 /* SAI Receive FIFO 6 */
 179 -#define FSL_SAI_RFR7   0xdc /* SAI Receive FIFO 7 */
 180 +#define FSL_SAI_RDR    0xa0 /* SAI Receive Data */
 181 +#define FSL_SAI_RFR    0xc0 /* SAI Receive FIFO */
 182  #define FSL_SAI_RMR    0xe0 /* SAI Receive Mask */
 183
 184  #define FSL_SAI_xCSR(tx)       (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)