projects / openwrt / staging / hauke.git / blob
? search:


d685119e0417b163bf5d3b0c63217d23e49b8c03
[openwrt/staging/hauke.git] /
1 From 2d6dfbd200d8de9bef8fb30bec90594acea9a145 Mon Sep 17 00:00:00 2001
2 From: Dong Aisheng <aisheng.dong@nxp.com>
3 Date: Fri, 16 Aug 2019 18:01:26 +0800
4 Subject: [PATCH] Revert "ASoC: fsl_sai: Add support for SAI new version"
5
6 This reverts commit 4f7a0728b5305e2d865f543fbcffd617e03c7674.
7 ---
8 sound/soc/fsl/fsl_sai.c | 228 ++++++++++++++++++++----------------------------
9 sound/soc/fsl/fsl_sai.h | 41 +++++----
10 2 files changed, 113 insertions(+), 156 deletions(-)
11
12 --- a/sound/soc/fsl/fsl_sai.c
13 +++ b/sound/soc/fsl/fsl_sai.c
14 @@ -40,7 +40,6 @@ static const struct snd_pcm_hw_constrain
15 static irqreturn_t fsl_sai_isr(int irq, void *devid)
16 {
17 struct fsl_sai *sai = (struct fsl_sai *)devid;
18 - unsigned int ofs = sai->soc_data->reg_offset;
19 struct device *dev = &sai->pdev->dev;
20 u32 flags, xcsr, mask;
21 bool irq_none = true;
22 @@ -53,7 +52,7 @@ static irqreturn_t fsl_sai_isr(int irq,
23 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
24
25 /* Tx IRQ */
26 - regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
27 + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
28 flags = xcsr & mask;
29
30 if (flags)
31 @@ -83,11 +82,11 @@ static irqreturn_t fsl_sai_isr(int irq,
32 xcsr &= ~FSL_SAI_CSR_xF_MASK;
33
34 if (flags)
35 - regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
36 + regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
37
38 irq_rx:
39 /* Rx IRQ */
40 - regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
41 + regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
42 flags = xcsr & mask;
43
44 if (flags)
45 @@ -117,7 +116,7 @@ irq_rx:
46 xcsr &= ~FSL_SAI_CSR_xF_MASK;
47
48 if (flags)
49 - regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
50 + regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
51
52 out:
53 if (irq_none)
54 @@ -141,7 +140,6 @@ static int fsl_sai_set_dai_sysclk_tr(str
55 int clk_id, unsigned int freq, int fsl_dir)
56 {
57 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
58 - unsigned int ofs = sai->soc_data->reg_offset;
59 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
60 u32 val_cr2 = 0;
61
62 @@ -162,7 +160,7 @@ static int fsl_sai_set_dai_sysclk_tr(str
63 return -EINVAL;
64 }
65
66 - regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
67 + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
68 FSL_SAI_CR2_MSEL_MASK, val_cr2);
69
70 return 0;
71 @@ -195,7 +193,6 @@ static int fsl_sai_set_dai_fmt_tr(struct
72 unsigned int fmt, int fsl_dir)
73 {
74 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
75 - unsigned int ofs = sai->soc_data->reg_offset;
76 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
77 u32 val_cr2 = 0, val_cr4 = 0;
78
79 @@ -290,9 +287,9 @@ static int fsl_sai_set_dai_fmt_tr(struct
80 return -EINVAL;
81 }
82
83 - regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
84 + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
85 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
86 - regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
87 + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
88 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
89 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
90
91 @@ -319,7 +316,6 @@ static int fsl_sai_set_dai_fmt(struct sn
92 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
93 {
94 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
95 - unsigned int ofs = sai->soc_data->reg_offset;
96 unsigned long clk_rate;
97 u32 savediv = 0, ratio, savesub = freq;
98 u32 id;
99 @@ -382,17 +378,17 @@ static int fsl_sai_set_bclk(struct snd_s
100 */
101 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
102 (!tx && !sai->synchronous[RX])) {
103 - regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
104 + regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
105 FSL_SAI_CR2_MSEL_MASK,
106 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
107 - regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
108 + regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
109 FSL_SAI_CR2_DIV_MASK, savediv - 1);
110 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
111 (tx && !sai->synchronous[TX])) {
112 - regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
113 + regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
114 FSL_SAI_CR2_MSEL_MASK,
115 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
116 - regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
117 + regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
118 FSL_SAI_CR2_DIV_MASK, savediv - 1);
119 }
120
121 @@ -407,7 +403,6 @@ static int fsl_sai_hw_params(struct snd_
122 struct snd_soc_dai *cpu_dai)
123 {
124 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
125 - unsigned int ofs = sai->soc_data->reg_offset;
126 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
127 unsigned int channels = params_channels(params);
128 u32 word_width = params_width(params);
129 @@ -460,19 +455,19 @@ static int fsl_sai_hw_params(struct snd_
130
131 if (!sai->is_slave_mode) {
132 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
133 - regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs),
134 + regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
135 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
136 val_cr4);
137 - regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),
138 + regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
139 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
140 FSL_SAI_CR5_FBT_MASK, val_cr5);
141 regmap_write(sai->regmap, FSL_SAI_TMR,
142 ~0UL - ((1 << channels) - 1));
143 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
144 - regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),
145 + regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
146 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
147 val_cr4);
148 - regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),
149 + regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
150 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
151 FSL_SAI_CR5_FBT_MASK, val_cr5);
152 regmap_write(sai->regmap, FSL_SAI_RMR,
153 @@ -480,10 +475,10 @@ static int fsl_sai_hw_params(struct snd_
154 }
155 }
156
157 - regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
158 + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
159 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
160 val_cr4);
161 - regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
162 + regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
163 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
164 FSL_SAI_CR5_FBT_MASK, val_cr5);
165 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
166 @@ -511,8 +506,6 @@ static int fsl_sai_trigger(struct snd_pc
167 struct snd_soc_dai *cpu_dai)
168 {
169 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
170 - unsigned int ofs = sai->soc_data->reg_offset;
171 -
172 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
173 u32 xcsr, count = 100;
174
175 @@ -521,9 +514,9 @@ static int fsl_sai_trigger(struct snd_pc
176 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
177 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
178 */
179 - regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
180 - sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
181 - regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
182 + regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
183 + sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
184 + regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
185 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
186
187 /*
188 @@ -534,44 +527,43 @@ static int fsl_sai_trigger(struct snd_pc
189 case SNDRV_PCM_TRIGGER_START:
190 case SNDRV_PCM_TRIGGER_RESUME:
191 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
192 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
193 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
194 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
195
196 - regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
197 + regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
198 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
199 - regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
200 + regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
201 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
202
203 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
204 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
205 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
206 break;
207 case SNDRV_PCM_TRIGGER_STOP:
208 case SNDRV_PCM_TRIGGER_SUSPEND:
209 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
210 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
211 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
212 FSL_SAI_CSR_FRDE, 0);
213 - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
214 + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
215 FSL_SAI_CSR_xIE_MASK, 0);
216
217 /* Check if the opposite FRDE is also disabled */
218 - regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
219 + regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
220 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
221 /* Disable both directions and reset their FIFOs */
222 - regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
223 + regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
224 FSL_SAI_CSR_TERE, 0);
225 - regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
226 + regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
227 FSL_SAI_CSR_TERE, 0);
228
229 /* TERE will remain set till the end of current frame */
230 do {
231 udelay(10);
232 - regmap_read(sai->regmap,
233 - FSL_SAI_xCSR(tx, ofs), &xcsr);
234 + regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
235 } while (--count && xcsr & FSL_SAI_CSR_TERE);
236
237 - regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
238 + regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
239 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
240 - regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
241 + regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
242 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
243
244 /*
245 @@ -583,13 +575,13 @@ static int fsl_sai_trigger(struct snd_pc
246 */
247 if (!sai->is_slave_mode) {
248 /* Software Reset for both Tx and Rx */
249 - regmap_write(sai->regmap, FSL_SAI_TCSR(ofs),
250 - FSL_SAI_CSR_SR);
251 - regmap_write(sai->regmap, FSL_SAI_RCSR(ofs),
252 - FSL_SAI_CSR_SR);
253 + regmap_write(sai->regmap,
254 + FSL_SAI_TCSR, FSL_SAI_CSR_SR);
255 + regmap_write(sai->regmap,
256 + FSL_SAI_RCSR, FSL_SAI_CSR_SR);
257 /* Clear SR bit to finish the reset */
258 - regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
259 - regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
260 + regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
261 + regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
262 }
263 }
264 break;
265 @@ -604,11 +596,10 @@ static int fsl_sai_startup(struct snd_pc
266 struct snd_soc_dai *cpu_dai)
267 {
268 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
269 - unsigned int ofs = sai->soc_data->reg_offset;
270 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
271 int ret;
272
273 - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
274 + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
275 FSL_SAI_CR3_TRCE_MASK,
276 FSL_SAI_CR3_TRCE);
277
278 @@ -622,10 +613,9 @@ static void fsl_sai_shutdown(struct snd_
279 struct snd_soc_dai *cpu_dai)
280 {
281 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
282 - unsigned int ofs = sai->soc_data->reg_offset;
283 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
284
285 - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
286 + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
287 FSL_SAI_CR3_TRCE_MASK, 0);
288 }
289
290 @@ -643,20 +633,17 @@ static const struct snd_soc_dai_ops fsl_
291 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
292 {
293 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
294 - unsigned int ofs = sai->soc_data->reg_offset;
295
296 /* Software Reset for both Tx and Rx */
297 - regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
298 - regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
299 + regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
300 + regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
301 /* Clear SR bit to finish the reset */
302 - regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
303 - regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
304 + regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
305 + regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
306
307 - regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
308 - FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
309 + regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
310 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
311 - regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
312 - FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
313 + regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
314 FSL_SAI_MAXBURST_RX - 1);
315
316 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
317 @@ -694,12 +681,12 @@ static const struct snd_soc_component_dr
318 .name = "fsl-sai",
319 };
320
321 -static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
322 - {FSL_SAI_TCR1(0), 0},
323 - {FSL_SAI_TCR2(0), 0},
324 - {FSL_SAI_TCR3(0), 0},
325 - {FSL_SAI_TCR4(0), 0},
326 - {FSL_SAI_TCR5(0), 0},
327 +static struct reg_default fsl_sai_reg_defaults[] = {
328 + {FSL_SAI_TCR1, 0},
329 + {FSL_SAI_TCR2, 0},
330 + {FSL_SAI_TCR3, 0},
331 + {FSL_SAI_TCR4, 0},
332 + {FSL_SAI_TCR5, 0},
333 {FSL_SAI_TDR0, 0},
334 {FSL_SAI_TDR1, 0},
335 {FSL_SAI_TDR2, 0},
336 @@ -708,50 +695,24 @@ static struct reg_default fsl_sai_reg_de
337 {FSL_SAI_TDR5, 0},
338 {FSL_SAI_TDR6, 0},
339 {FSL_SAI_TDR7, 0},
340 - {FSL_SAI_TMR, 0},
341 - {FSL_SAI_RCR1(0), 0},
342 - {FSL_SAI_RCR2(0), 0},
343 - {FSL_SAI_RCR3(0), 0},
344 - {FSL_SAI_RCR4(0), 0},
345 - {FSL_SAI_RCR5(0), 0},
346 - {FSL_SAI_RMR, 0},
347 -};
348 -
349 -static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
350 - {FSL_SAI_TCR1(8), 0},
351 - {FSL_SAI_TCR2(8), 0},
352 - {FSL_SAI_TCR3(8), 0},
353 - {FSL_SAI_TCR4(8), 0},
354 - {FSL_SAI_TCR5(8), 0},
355 - {FSL_SAI_TDR0, 0},
356 - {FSL_SAI_TDR1, 0},
357 - {FSL_SAI_TDR2, 0},
358 - {FSL_SAI_TDR3, 0},
359 - {FSL_SAI_TDR4, 0},
360 - {FSL_SAI_TDR5, 0},
361 - {FSL_SAI_TDR6, 0},
362 - {FSL_SAI_TDR7, 0},
363 - {FSL_SAI_TMR, 0},
364 - {FSL_SAI_RCR1(8), 0},
365 - {FSL_SAI_RCR2(8), 0},
366 - {FSL_SAI_RCR3(8), 0},
367 - {FSL_SAI_RCR4(8), 0},
368 - {FSL_SAI_RCR5(8), 0},
369 - {FSL_SAI_RMR, 0},
370 + {FSL_SAI_TMR, 0},
371 + {FSL_SAI_RCR1, 0},
372 + {FSL_SAI_RCR2, 0},
373 + {FSL_SAI_RCR3, 0},
374 + {FSL_SAI_RCR4, 0},
375 + {FSL_SAI_RCR5, 0},
376 + {FSL_SAI_RMR, 0},
377 };
378
379 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
380 {
381 - struct fsl_sai *sai = dev_get_drvdata(dev);
382 - unsigned int ofs = sai->soc_data->reg_offset;
383 -
384 - if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
385 - return true;
386 -
387 - if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
388 - return true;
389 -
390 switch (reg) {
391 + case FSL_SAI_TCSR:
392 + case FSL_SAI_TCR1:
393 + case FSL_SAI_TCR2:
394 + case FSL_SAI_TCR3:
395 + case FSL_SAI_TCR4:
396 + case FSL_SAI_TCR5:
397 case FSL_SAI_TFR0:
398 case FSL_SAI_TFR1:
399 case FSL_SAI_TFR2:
400 @@ -761,6 +722,12 @@ static bool fsl_sai_readable_reg(struct
401 case FSL_SAI_TFR6:
402 case FSL_SAI_TFR7:
403 case FSL_SAI_TMR:
404 + case FSL_SAI_RCSR:
405 + case FSL_SAI_RCR1:
406 + case FSL_SAI_RCR2:
407 + case FSL_SAI_RCR3:
408 + case FSL_SAI_RCR4:
409 + case FSL_SAI_RCR5:
410 case FSL_SAI_RDR0:
411 case FSL_SAI_RDR1:
412 case FSL_SAI_RDR2:
413 @@ -786,13 +753,9 @@ static bool fsl_sai_readable_reg(struct
414
415 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
416 {
417 - struct fsl_sai *sai = dev_get_drvdata(dev);
418 - unsigned int ofs = sai->soc_data->reg_offset;
419 -
420 - if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
421 - return true;
422 -
423 switch (reg) {
424 + case FSL_SAI_TCSR:
425 + case FSL_SAI_RCSR:
426 case FSL_SAI_TFR0:
427 case FSL_SAI_TFR1:
428 case FSL_SAI_TFR2:
429 @@ -825,16 +788,13 @@ static bool fsl_sai_volatile_reg(struct
430
431 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
432 {
433 - struct fsl_sai *sai = dev_get_drvdata(dev);
434 - unsigned int ofs = sai->soc_data->reg_offset;
435 -
436 - if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
437 - return true;
438 -
439 - if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
440 - return true;
441 -
442 switch (reg) {
443 + case FSL_SAI_TCSR:
444 + case FSL_SAI_TCR1:
445 + case FSL_SAI_TCR2:
446 + case FSL_SAI_TCR3:
447 + case FSL_SAI_TCR4:
448 + case FSL_SAI_TCR5:
449 case FSL_SAI_TDR0:
450 case FSL_SAI_TDR1:
451 case FSL_SAI_TDR2:
452 @@ -844,6 +804,12 @@ static bool fsl_sai_writeable_reg(struct
453 case FSL_SAI_TDR6:
454 case FSL_SAI_TDR7:
455 case FSL_SAI_TMR:
456 + case FSL_SAI_RCSR:
457 + case FSL_SAI_RCR1:
458 + case FSL_SAI_RCR2:
459 + case FSL_SAI_RCR3:
460 + case FSL_SAI_RCR4:
461 + case FSL_SAI_RCR5:
462 case FSL_SAI_RMR:
463 return true;
464 default:
465 @@ -851,15 +817,15 @@ static bool fsl_sai_writeable_reg(struct
466 }
467 }
468
469 -static struct regmap_config fsl_sai_regmap_config = {
470 +static const struct regmap_config fsl_sai_regmap_config = {
471 .reg_bits = 32,
472 .reg_stride = 4,
473 .val_bits = 32,
474 .fast_io = true,
475
476 .max_register = FSL_SAI_RMR,
477 - .reg_defaults = fsl_sai_reg_defaults_ofs0,
478 - .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
479 + .reg_defaults = fsl_sai_reg_defaults,
480 + .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
481 .readable_reg = fsl_sai_readable_reg,
482 .volatile_reg = fsl_sai_volatile_reg,
483 .writeable_reg = fsl_sai_writeable_reg,
484 @@ -891,12 +857,6 @@ static int fsl_sai_probe(struct platform
485 if (IS_ERR(base))
486 return PTR_ERR(base);
487
488 - if (sai->soc_data->reg_offset == 8) {
489 - fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
490 - fsl_sai_regmap_config.num_reg_defaults =
491 - ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
492 - }
493 -
494 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
495 "bus", base, &fsl_sai_regmap_config);
496
497 @@ -1026,13 +986,11 @@ static int fsl_sai_remove(struct platfor
498 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
499 .use_imx_pcm = false,
500 .fifo_depth = 32,
501 - .reg_offset = 0,
502 };
503
504 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
505 .use_imx_pcm = true,
506 .fifo_depth = 32,
507 - .reg_offset = 0,
508 };
509
510 static const struct of_device_id fsl_sai_ids[] = {
511 @@ -1065,7 +1023,6 @@ static int fsl_sai_runtime_suspend(struc
512 static int fsl_sai_runtime_resume(struct device *dev)
513 {
514 struct fsl_sai *sai = dev_get_drvdata(dev);
515 - unsigned int ofs = sai->soc_data->reg_offset;
516 int ret;
517
518 ret = clk_prepare_enable(sai->bus_clk);
519 @@ -1087,11 +1044,11 @@ static int fsl_sai_runtime_resume(struct
520 }
521
522 regcache_cache_only(sai->regmap, false);
523 - regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
524 - regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
525 + regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
526 + regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
527 usleep_range(1000, 2000);
528 - regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
529 - regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
530 + regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
531 + regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
532
533 ret = regcache_sync(sai->regmap);
534 if (ret)
535 --- a/sound/soc/fsl/fsl_sai.h
536 +++ b/sound/soc/fsl/fsl_sai.h
537 @@ -14,12 +14,12 @@
538 SNDRV_PCM_FMTBIT_S32_LE)
539
540 /* SAI Register Map Register */
541 -#define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
542 -#define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
543 -#define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
544 -#define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */
545 -#define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */
546 -#define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */
547 +#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */
548 +#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */
549 +#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */
550 +#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
551 +#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
552 +#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
553 #define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
554 #define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
555 #define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
556 @@ -37,12 +37,12 @@
557 #define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
558 #define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
559 #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
560 -#define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
561 -#define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
562 -#define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
563 -#define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
564 -#define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
565 -#define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
566 +#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
567 +#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
568 +#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */
569 +#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
570 +#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
571 +#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
572 #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
573 #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
574 #define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
575 @@ -61,14 +61,14 @@
576 #define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
577 #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
578
579 -#define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
580 -#define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
581 -#define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs))
582 -#define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs))
583 -#define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs))
584 -#define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs))
585 -#define FSL_SAI_xDR0(tx) (tx ? FSL_SAI_TDR0 : FSL_SAI_RDR0)
586 -#define FSL_SAI_xFR0(tx) (tx ? FSL_SAI_TFR0 : FSL_SAI_RFR0)
587 +#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
588 +#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1)
589 +#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2)
590 +#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3)
591 +#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4)
592 +#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5)
593 +#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR)
594 +#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR)
595 #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
596
597 /* SAI Transmit/Receive Control Register */
598 @@ -158,7 +158,6 @@
599 struct fsl_sai_soc_data {
600 bool use_imx_pcm;
601 unsigned int fifo_depth;
602 - unsigned int reg_offset;
603 };
604
605 struct fsl_sai {
Hauke Mehrtens staging tree